[llvm] 3a98bf9 - [AMDGPU][NFC] Eliminate unnecessary TableGen casts. (#71802)
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Fri Nov 10 06:01:39 PST 2023
Author: Ivan Kosarev
Date: 2023-11-10T14:01:35Z
New Revision: 3a98bf92d0faf021bdfaef90f8bc2780f273c929
URL: https://github.com/llvm/llvm-project/commit/3a98bf92d0faf021bdfaef90f8bc2780f273c929
DIFF: https://github.com/llvm/llvm-project/commit/3a98bf92d0faf021bdfaef90f8bc2780f273c929.diff
LOG: [AMDGPU][NFC] Eliminate unnecessary TableGen casts. (#71802)
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 8e42a4a454a70cb..095b014173cb31b 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -353,23 +353,23 @@ foreach Type = ["I", "U"] in
(!cast<Extract>(Type#Index#"_4bit") node:$src1))>;
}
-class UDot2Pat<Instruction Inst> : GCNPat <
+class UDot2Pat<VOP_Pseudo Inst> : GCNPat <
(add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)),
(srl i32:$src1, (i32 16))), i32:$src2),
(AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)),
(and i32:$src1, (i32 65535)))
),
(Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> {
- let Predicates = !cast<VOP_Pseudo>(Inst).Predicates;
+ let Predicates = Inst.Predicates;
}
-class SDot2Pat<Instruction Inst> : GCNPat <
+class SDot2Pat<VOP_Pseudo Inst> : GCNPat <
(add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)),
(sra i32:$src1, (i32 16))), i32:$src2),
(AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16),
(sext_inreg i32:$src1, i16))),
(Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> {
- let Predicates = !cast<VOP_Pseudo>(Inst).Predicates;
+ let Predicates = Inst.Predicates;
}
let IsDOT = 1 in {
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