[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Valery Pykhtin via llvm-commits]

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@@ -1184,8 +1184,7 @@ bool ILPInitialScheduleStage::shouldRevertScheduling(unsigned WavesAfter) {
 
 bool GCNSchedStage::mayCauseSpilling(unsigned WavesAfter) {
   if (WavesAfter <= MFI.getMinWavesPerEU() &&
-      !PressureAfter.less(ST, PressureBefore) &&
-      isRegionWithExcessRP()) {
+      !PressureAfter.less(ST, MFI, PressureBefore) && isRegionWithExcessRP()) {
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vpykhtin wrote:

We should probably decide which kind of register excess is important here and compare schedules accordingly. 

https://github.com/llvm/llvm-project/pull/71882