[llvm] [PowerPC]redesign the target flags (PR #69695)
Chen Zheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 9 23:05:05 PST 2023
https://github.com/chenzheng1030 updated https://github.com/llvm/llvm-project/pull/69695
>From d313dfd35051d599f82a17e12f5080613c4fcc83 Mon Sep 17 00:00:00 2001
From: Chen Zheng <czhengsz at cn.ibm.com>
Date: Fri, 20 Oct 2023 03:54:52 -0400
Subject: [PATCH 1/2] redesign the target flags for ppc
---
llvm/lib/Target/PowerPC/PPC.h | 72 ++++++++++++-------
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 29 +++-----
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 16 ++---
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 37 +++++-----
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 30 +++++++-
llvm/lib/Target/PowerPC/PPCMCInstLower.cpp | 19 +++--
.../lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp | 2 +-
.../test/CodeGen/PowerPC/aix-tls-gd-double.ll | 32 ++++-----
.../PowerPC/aix-tls-gd-target-flags.ll | 4 +-
llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll | 4 +-
llvm/test/CodeGen/PowerPC/tls-crash.mir | 4 +-
12 files changed, 144 insertions(+), 107 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 086b61a93a43d73..79b90dfa2be85b3 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -102,79 +102,99 @@ class ModulePass;
// PPC Specific MachineOperand flags.
MO_NO_FLAG,
+ /// On PPC, the 12 bits are not enough for all target operand flags.
+ /// Treat all PPC target flags as direct flags. This also means we can not
+ /// use a bitmask flag, so if one operand has two or more flags, a fake
+ /// combination flag must be created. See example MO_GOT_TPREL_PCREL_FLAG.
+
/// On a symbol operand "FOO", this indicates that the reference is actually
/// to "FOO at plt". This is used for calls and jumps to external functions
/// and for PIC calls on 32-bit ELF systems.
- MO_PLT = 1,
+ MO_PLT,
/// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
/// the function's picbase, e.g. lo16(symbol-picbase).
- MO_PIC_FLAG = 2,
+ MO_PIC_FLAG,
/// MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to
/// the current instruction address(pc), e.g., var at pcrel. Fixup is VK_PCREL.
- MO_PCREL_FLAG = 4,
+ MO_PCREL_FLAG,
/// MO_GOT_FLAG - If this bit is set the symbol reference is to be computed
/// via the GOT. For example when combined with the MO_PCREL_FLAG it should
/// produce the relocation @got at pcrel. Fixup is VK_PPC_GOT_PCREL.
- MO_GOT_FLAG = 8,
+ MO_GOT_FLAG,
- // MO_PCREL_OPT_FLAG - If this bit is set the operand is part of a
- // PC Relative linker optimization.
- MO_PCREL_OPT_FLAG = 16,
+ /// MO_PCREL_OPT_FLAG - If this bit is set the operand is part of a
+ /// PC Relative linker optimization.
+ MO_PCREL_OPT_FLAG,
/// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
/// TLS General Dynamic model for Linux and the variable offset of TLS
/// General Dynamic model for AIX.
- MO_TLSGD_FLAG = 32,
+ MO_TLSGD_FLAG,
/// MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to
/// the thread pointer and the symbol can be used for the TLS Initial Exec
/// and Local Exec models.
- MO_TPREL_FLAG = 64,
+ MO_TPREL_FLAG,
/// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to
/// TLS Local Dynamic model.
- MO_TLSLD_FLAG = 128,
+ MO_TLSLD_FLAG,
/// MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative
/// to the region handle of TLS General Dynamic model for AIX.
- MO_TLSGDM_FLAG = 256,
+ MO_TLSGDM_FLAG,
/// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
/// they should produce the relocation @got at tlsgd@pcrel.
/// Fix up is VK_PPC_GOT_TLSGD_PCREL
- MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
+ /// MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
+ MO_GOT_TLSGD_PCREL_FLAG,
/// MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set
/// they should produce the relocation @got at tlsld@pcrel.
/// Fix up is VK_PPC_GOT_TLSLD_PCREL
- MO_GOT_TLSLD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSLD_FLAG,
+ /// MO_GOT_TLSLD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSLD_FLAG,
+ MO_GOT_TLSLD_PCREL_FLAG,
/// MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set
/// they should produce the relocation @got at tprel@pcrel.
/// Fix up is VK_PPC_GOT_TPREL_PCREL
- MO_GOT_TPREL_PCREL_FLAG = MO_GOT_FLAG | MO_TPREL_FLAG | MO_PCREL_FLAG,
-
- /// The next are not flags but distinct values.
- MO_ACCESS_MASK = 0xf00,
+ /// MO_GOT_TPREL_PCREL_FLAG = MO_GOT_FLAG | MO_TPREL_FLAG | MO_PCREL_FLAG,
+ MO_GOT_TPREL_PCREL_FLAG,
/// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
- MO_LO = 1 << 8,
- MO_HA = 2 << 8,
+ MO_LO,
+ MO_HA,
- MO_TPREL_LO = 4 << 8,
- MO_TPREL_HA = 3 << 8,
+ MO_TPREL_LO,
+ MO_TPREL_HA,
/// These values identify relocations on immediates folded
/// into memory operations.
- MO_DTPREL_LO = 5 << 8,
- MO_TLSLD_LO = 6 << 8,
- MO_TOC_LO = 7 << 8,
+ MO_DTPREL_LO,
+ MO_TLSLD_LO,
+ MO_TOC_LO,
+
+ /// Symbol for VK_PPC_TLS fixup attached to an ADD instruction
+ MO_TLS,
+
+ /// MO_PIC_HA_FLAG = MO_PIC_FLAG | MO_HA
+ MO_PIC_HA_FLAG,
+
+ /// MO_PIC_LO_FLAG = MO_PIC_FLAG | MO_LO
+ MO_PIC_LO_FLAG,
+
+ /// MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TPREL_FLAG
+ MO_TPREL_PCREL_FLAG,
+
+ /// MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TLS
+ MO_TLS_PCREL_FLAG,
- // Symbol for VK_PPC_TLS fixup attached to an ADD instruction
- MO_TLS = 8 << 8
+ /// MO_GOT_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG
+ MO_GOT_PCREL_FLAG,
};
} // end namespace PPCII
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 4f15ba497d84c45..fcbd7f3256f867c 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -715,25 +715,11 @@ static MCSymbol *getMCSymbolForTOCPseudoMO(const MachineOperand &MO,
}
}
-static bool hasTLSFlag(const MachineOperand &MO) {
- unsigned Flags = MO.getTargetFlags();
- if (Flags & PPCII::MO_TLSGD_FLAG || Flags & PPCII::MO_TPREL_FLAG ||
- Flags & PPCII::MO_TLSLD_FLAG || Flags & PPCII::MO_TLSGDM_FLAG)
- return true;
-
- if (Flags == PPCII::MO_TPREL_LO || Flags == PPCII::MO_TPREL_HA ||
- Flags == PPCII::MO_DTPREL_LO || Flags == PPCII::MO_TLSLD_LO ||
- Flags == PPCII::MO_TLS)
- return true;
-
- return false;
-}
-
static PPCAsmPrinter::TOCEntryType
getTOCEntryTypeForMO(const MachineOperand &MO) {
// Use the target flags to determine if this MO is Thread Local.
// If we don't do this it comes out as Global.
- if (hasTLSFlag(MO))
+ if (PPCInstrInfo::hasTLSFlag(MO.getTargetFlags()))
return PPCAsmPrinter::TOCType_ThreadLocal;
switch (MO.getType()) {
@@ -830,7 +816,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// For TLS initial-exec and local-exec accesses on AIX, we have one TOC
// entry for the symbol (with the variable offset), which is differentiated
// by MO_TPREL_FLAG.
- if (MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) {
+ if (MO.getTargetFlags() == PPCII::MO_TPREL_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_TPREL_PCREL_FLAG) {
assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
if (Model == TLSModel::LocalExec)
@@ -842,9 +830,10 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// For GD TLS access on AIX, we have two TOC entries for the symbol (one for
// the variable offset and the other for the region handle). They are
// differentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
- if (MO.getTargetFlags() & PPCII::MO_TLSGDM_FLAG)
+ if (MO.getTargetFlags() == PPCII::MO_TLSGDM_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
- if (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG)
+ if (MO.getTargetFlags() == PPCII::MO_TLSGD_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
return MCSymbolRefExpr::VariantKind::VK_None;
};
@@ -1539,7 +1528,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// with an immediate operand having the MO_TPREL_FLAG. Such an instruction
// does not otherwise arise.
const MachineOperand &MO = MI->getOperand(2);
- if ((MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) != 0) {
+ if (MO.getTargetFlags() == PPCII::MO_TPREL_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_TPREL_PCREL_FLAG) {
assert(
Subtarget->hasAIXSmallLocalExecTLS() &&
"addi with thread-pointer only expected with local-exec small TLS");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 5e0c2d62f5a9cb5..f53281006522caf 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2971,7 +2971,7 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
template <typename Ty> static bool isValidPCRelNode(SDValue N) {
Ty *PCRelCand = dyn_cast<Ty>(N);
- return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
+ return PCRelCand && (PPCInstrInfo::hasPCRelFlag(PCRelCand->getTargetFlags()));
}
/// Returns true if this address is a PC Relative address.
@@ -3132,8 +3132,8 @@ static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
// Don't use the pic base if not in PIC relocation model.
if (IsPIC) {
- HiOpFlags |= PPCII::MO_PIC_FLAG;
- LoOpFlags |= PPCII::MO_PIC_FLAG;
+ HiOpFlags = PPCII::MO_PIC_HA_FLAG;
+ LoOpFlags = PPCII::MO_PIC_LO_FLAG;
}
}
@@ -3452,8 +3452,8 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
if (Model == TLSModel::LocalExec) {
if (Subtarget.isUsingPCRelativeCalls()) {
SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
- SDValue TGA = DAG.getTargetGlobalAddress(
- GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
+ SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
+ PPCII::MO_TPREL_PCREL_FLAG);
SDValue MatAddr =
DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
@@ -3475,8 +3475,7 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
SDValue TGA = DAG.getTargetGlobalAddress(
GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
SDValue TGATLS = DAG.getTargetGlobalAddress(
- GV, dl, PtrVT, 0,
- IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
+ GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_TLS_PCREL_FLAG : PPCII::MO_TLS);
SDValue TPOffset;
if (IsPCRel) {
SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
@@ -3572,8 +3571,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
EVT Ty = getPointerTy(DAG.getDataLayout());
if (isAccessedAsGotIndirect(Op)) {
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
- PPCII::MO_PCREL_FLAG |
- PPCII::MO_GOT_FLAG);
+ PPCII::MO_GOT_PCREL_FLAG);
SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
MachinePointerInfo());
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 75c6399fe7e16b1..22503a47cbced1a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2973,27 +2973,12 @@ unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
std::pair<unsigned, unsigned>
PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
- const unsigned Mask = PPCII::MO_ACCESS_MASK;
- return std::make_pair(TF & Mask, TF & ~Mask);
+ // PPC always uses a direct mask.
+ return std::make_pair(TF, 0u);
}
ArrayRef<std::pair<unsigned, const char *>>
PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
- using namespace PPCII;
- static const std::pair<unsigned, const char *> TargetFlags[] = {
- {MO_LO, "ppc-lo"},
- {MO_HA, "ppc-ha"},
- {MO_TPREL_LO, "ppc-tprel-lo"},
- {MO_TPREL_HA, "ppc-tprel-ha"},
- {MO_DTPREL_LO, "ppc-dtprel-lo"},
- {MO_TLSLD_LO, "ppc-tlsld-lo"},
- {MO_TOC_LO, "ppc-toc-lo"},
- {MO_TLS, "ppc-tls"}};
- return ArrayRef(TargetFlags);
-}
-
-ArrayRef<std::pair<unsigned, const char *>>
-PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
using namespace PPCII;
static const std::pair<unsigned, const char *> TargetFlags[] = {
{MO_PLT, "ppc-plt"},
@@ -3002,12 +2987,26 @@ PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
{MO_GOT_FLAG, "ppc-got"},
{MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
{MO_TLSGD_FLAG, "ppc-tlsgd"},
- {MO_TLSLD_FLAG, "ppc-tlsld"},
{MO_TPREL_FLAG, "ppc-tprel"},
+ {MO_TLSLD_FLAG, "ppc-tlsld"},
{MO_TLSGDM_FLAG, "ppc-tlsgdm"},
{MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
{MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
- {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
+ {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"},
+ {MO_LO, "ppc-lo"},
+ {MO_HA, "ppc-ha"},
+ {MO_TPREL_LO, "ppc-tprel-lo"},
+ {MO_TPREL_HA, "ppc-tprel-ha"},
+ {MO_DTPREL_LO, "ppc-dtprel-lo"},
+ {MO_TLSLD_LO, "ppc-tlsld-lo"},
+ {MO_TOC_LO, "ppc-toc-lo"},
+ {MO_TLS, "ppc-tls"},
+ {MO_PIC_HA_FLAG, "ppc-ha-pic"},
+ {MO_PIC_LO_FLAG, "ppc-lo-pic"},
+ {MO_TPREL_PCREL_FLAG, "ppc-tprel-pcrel"},
+ {MO_TLS_PCREL_FLAG, "ppc-tls-pcrel"},
+ {MO_GOT_PCREL_FLAG, "ppc-got-pcrel"},
+ };
return ArrayRef(TargetFlags);
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 1f59e994d9cb1ad..d57cba9b4d599e3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -14,6 +14,7 @@
#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
#include "MCTargetDesc/PPCMCTargetDesc.h"
+#include "PPC.h"
#include "PPCRegisterInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -283,6 +284,32 @@ class PPCInstrInfo : public PPCGenInstrInfo {
return false;
}
+ static bool hasPCRelFlag(unsigned TF) {
+ return TF == PPCII::MO_PCREL_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_PCREL_FLAG;
+ }
+
+ static bool hasGOTFlag(unsigned TF) {
+ return TF == PPCII::MO_GOT_FLAG || TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_PCREL_FLAG;
+ }
+
+ static bool hasTLSFlag(unsigned TF) {
+ return TF == PPCII::MO_TLSGD_FLAG || TF == PPCII::MO_TPREL_FLAG ||
+ TF == PPCII::MO_TLSLD_FLAG || TF == PPCII::MO_TLSGDM_FLAG ||
+ TF == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TLSLD_PCREL_FLAG ||
+ TF == PPCII::MO_GOT_TPREL_PCREL_FLAG || TF == PPCII::MO_TPREL_LO ||
+ TF == PPCII::MO_TPREL_HA || TF == PPCII::MO_DTPREL_LO ||
+ TF == PPCII::MO_TLSLD_LO || TF == PPCII::MO_TLS ||
+ TF == PPCII::MO_TPREL_PCREL_FLAG || TF == PPCII::MO_TLS_PCREL_FLAG;
+ }
+
ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
const ScheduleDAG *DAG) const override;
@@ -555,9 +582,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const override;
- ArrayRef<std::pair<unsigned, const char *>>
- getSerializableBitmaskMachineOperandTargetFlags() const override;
-
// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
bool expandVSXMemPseudo(MachineInstr &MI) const;
diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
index c9797fdc22863df..9a3ca5a7829362b 100644
--- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -54,7 +54,7 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
MCContext &Ctx = Printer.OutContext;
MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
- unsigned access = MO.getTargetFlags() & PPCII::MO_ACCESS_MASK;
+ unsigned access = MO.getTargetFlags();
switch (access) {
case PPCII::MO_TPREL_LO:
@@ -73,9 +73,10 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
RefKind = MCSymbolRefExpr::VK_PPC_TOC_LO;
break;
case PPCII::MO_TLS:
- bool IsPCRel = (MO.getTargetFlags() & ~access) == PPCII::MO_PCREL_FLAG;
- RefKind = IsPCRel ? MCSymbolRefExpr::VK_PPC_TLS_PCREL
- : MCSymbolRefExpr::VK_PPC_TLS;
+ RefKind = MCSymbolRefExpr::VK_PPC_TLS;
+ break;
+ case PPCII::MO_TLS_PCREL_FLAG:
+ RefKind = MCSymbolRefExpr::VK_PPC_TLS_PCREL;
break;
}
@@ -85,9 +86,9 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
RefKind = MCSymbolRefExpr::VK_PLT;
else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
RefKind = MCSymbolRefExpr::VK_PCREL;
- else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_GOT_FLAG))
+ else if (MO.getTargetFlags() == PPCII::MO_GOT_PCREL_FLAG)
RefKind = MCSymbolRefExpr::VK_PPC_GOT_PCREL;
- else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG))
+ else if (MO.getTargetFlags() == PPCII::MO_TPREL_PCREL_FLAG)
RefKind = MCSymbolRefExpr::VK_TPREL;
else if (MO.getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
RefKind = MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL;
@@ -138,7 +139,9 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
Ctx);
// Subtract off the PIC base if required.
- if (MO.getTargetFlags() & PPCII::MO_PIC_FLAG) {
+ if (MO.getTargetFlags() == PPCII::MO_PIC_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_PIC_HA_FLAG ||
+ MO.getTargetFlags() == PPCII::MO_PIC_LO_FLAG) {
const MachineFunction *MF = MO.getParent()->getParent()->getParent();
const MCExpr *PB = MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
@@ -148,9 +151,11 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
// Add ha16() / lo16() markers if required.
switch (access) {
case PPCII::MO_LO:
+ case PPCII::MO_PIC_LO_FLAG:
Expr = PPCMCExpr::createLo(Expr, Ctx);
break;
case PPCII::MO_HA:
+ case PPCII::MO_PIC_HA_FLAG:
Expr = PPCMCExpr::createHa(Expr, Ctx);
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index 647f8a7475813bd..ce8d11de3c322cc 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -240,7 +240,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
return false;
// Finally return true only if the GOT flag is present.
- return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
+ return PPCInstrInfo::hasGOTFlag(SymbolOp.getTargetFlags());
}
bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
diff --git a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
index 8120975c4fb257a..81f078ab246e6ab 100644
--- a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
@@ -100,7 +100,7 @@ namespace {
return true;
for (const MachineOperand &MO : MI.operands()) {
- if ((MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) == PPCII::MO_TOC_LO)
+ if (MO.getTargetFlags() == PPCII::MO_TOC_LO)
return true;
}
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
index 46ce3bfd450bd0d..c0ffb8154c6917f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
@@ -24,7 +24,7 @@ define void @storesTGUninit(double %Val) #0 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
+; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGUninit
; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -54,7 +54,7 @@ define void @storesTGUninit(double %Val) #0 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
+; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGUninit
; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -90,7 +90,7 @@ define void @storesTGInit(double %Val) #0 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
+; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsgdm) @TGInit
; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -120,7 +120,7 @@ define void @storesTGInit(double %Val) #0 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
+; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsgdm) @TGInit
; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -156,7 +156,7 @@ define void @storesTIInit(double %Val) #0 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
+; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit
; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -186,7 +186,7 @@ define void @storesTIInit(double %Val) #0 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
+; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit
; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -222,7 +222,7 @@ define void @storesTWInit(double %Val) #0 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
+; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-tlsgdm) @TWInit
; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -252,7 +252,7 @@ define void @storesTWInit(double %Val) #0 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
+; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-tlsgdm) @TWInit
; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -288,7 +288,7 @@ define double @loadsTGUninit() #1 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
+; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGUninit
; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -325,7 +325,7 @@ define double @loadsTGUninit() #1 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
+; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGUninit
; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -370,7 +370,7 @@ define double @loadsTGInit() #1 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
+; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsgdm) @TGInit
; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -407,7 +407,7 @@ define double @loadsTGInit() #1 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
+; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsgdm) @TGInit
; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -452,7 +452,7 @@ define double @loadsTIInit() #1 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
+; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit
; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -489,7 +489,7 @@ define double @loadsTIInit() #1 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
+; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-tlsgdm) @TIInit
; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
@@ -534,7 +534,7 @@ define double @loadsTWInit() #1 {
; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stwu 1, -32(1)
-; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
+; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-tlsgdm) @TWInit
; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR]
@@ -571,7 +571,7 @@ define double @loadsTWInit() #1 {
; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: stdu 1, -48(1)
-; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
+; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-tlsgdm) @TWInit
; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR]
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-gd-target-flags.ll b/llvm/test/CodeGen/PowerPC/aix-tls-gd-target-flags.ll
index f52e213fee58fb0..f55932c3088de9b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-gd-target-flags.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-gd-target-flags.ll
@@ -8,11 +8,11 @@
define signext i32 @foo() {
; CHECK-LABEL: name: foo
; CHECK: bb.0.entry:
- ; CHECK-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-lo) @a, $x2 :: (load (s64) from got)
+ ; CHECK-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgdm) @a, $x2 :: (load (s64) from got)
; CHECK-NEXT: [[LDtoc1:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @a, $x2 :: (load (s64) from got)
; CHECK-NEXT: [[TLSGDAIX8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = TLSGDAIX8 killed [[LDtoc1]], killed [[LDtoc]]
; CHECK-NEXT: [[LWZ:%[0-9]+]]:gprc = LWZ 0, killed [[TLSGDAIX8_]] :: (dereferenceable load (s32) from @a)
- ; CHECK-NEXT: [[LDtoc2:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-lo) @b, $x2 :: (load (s64) from got)
+ ; CHECK-NEXT: [[LDtoc2:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgdm) @b, $x2 :: (load (s64) from got)
; CHECK-NEXT: [[LDtoc3:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @b, $x2 :: (load (s64) from got)
; CHECK-NEXT: [[TLSGDAIX8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = TLSGDAIX8 killed [[LDtoc3]], killed [[LDtoc2]]
; CHECK-NEXT: [[LWZ1:%[0-9]+]]:gprc = LWZ 0, killed [[TLSGDAIX8_1]] :: (dereferenceable load (s32) from @b)
diff --git a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
index 2fcc67087468d5f..e7c49c9dcc7d998 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
@@ -375,7 +375,7 @@ define i32 @test4(i32 %inp) {
; AIX64-NEXT: B %bb.2
; AIX64-NEXT: {{ $}}
; AIX64-NEXT: bb.2.return:
- ; AIX64-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-lo) @tls_var, $x2 :: (load (s64) from got)
+ ; AIX64-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgdm) @tls_var, $x2 :: (load (s64) from got)
; AIX64-NEXT: [[LDtoc1:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @tls_var, $x2 :: (load (s64) from got)
; AIX64-NEXT: [[TLSGDAIX8_:%[0-9]+]]:g8rc = TLSGDAIX8 killed [[LDtoc1]], killed [[LDtoc]]
; AIX64-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[TLSGDAIX8_]].sub_32
@@ -405,7 +405,7 @@ define i32 @test4(i32 %inp) {
; AIX32-NEXT: B %bb.2
; AIX32-NEXT: {{ $}}
; AIX32-NEXT: bb.2.return:
- ; AIX32-NEXT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-lo) @tls_var, $r2 :: (load (s32) from got)
+ ; AIX32-NEXT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgdm) @tls_var, $r2 :: (load (s32) from got)
; AIX32-NEXT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgd) @tls_var, $r2 :: (load (s32) from got)
; AIX32-NEXT: [[TLSGDAIX:%[0-9]+]]:gprc = TLSGDAIX killed [[LWZtoc1]], killed [[LWZtoc]]
; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[TLSGDAIX]], [[ISEL]]
diff --git a/llvm/test/CodeGen/PowerPC/tls-crash.mir b/llvm/test/CodeGen/PowerPC/tls-crash.mir
index 186ba6da325a918..aa08790b36c9ec1 100644
--- a/llvm/test/CodeGen/PowerPC/tls-crash.mir
+++ b/llvm/test/CodeGen/PowerPC/tls-crash.mir
@@ -18,8 +18,8 @@ body: |
liveins: $x3
%0:g8rc = COPY killed $x3
- %1:g8rc_and_g8rc_nox0 = PADDI8pc 0, target-flags(ppc-pcrel, ppc-got, ppc-tlsld) @x
- %2:g8rc_and_g8rc_nox0 = PADDIdtprel killed %1, target-flags(ppc-pcrel, ppc-got, ppc-tlsld) @x
+ %1:g8rc_and_g8rc_nox0 = PADDI8pc 0, target-flags(ppc-got-tlsld-pcrel) @x
+ %2:g8rc_and_g8rc_nox0 = PADDIdtprel killed %1, target-flags(ppc-got-tlsld-pcrel) @x
STD killed %0, 0, killed %2 :: (store (s64) into `i8** bitcast (%0** @x to i8**)`)
BLR8 implicit $lr8, implicit $rm
...
>From bf09a2d50955e95e969cf35482f4e991a5496abb Mon Sep 17 00:00:00 2001
From: Chen Zheng <czhengsz at cn.ibm.com>
Date: Fri, 10 Nov 2023 02:04:46 -0500
Subject: [PATCH 2/2] address comments
---
llvm/lib/Target/PowerPC/PPC.h | 6 +++---
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 20 ++++++++++----------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 79b90dfa2be85b3..c870545f5b92cb1 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -103,9 +103,9 @@ class ModulePass;
MO_NO_FLAG,
/// On PPC, the 12 bits are not enough for all target operand flags.
- /// Treat all PPC target flags as direct flags. This also means we can not
- /// use a bitmask flag, so if one operand has two or more flags, a fake
- /// combination flag must be created. See example MO_GOT_TPREL_PCREL_FLAG.
+ /// Treat all PPC target flags as direct flags. To define new flag, add new
+ /// enum entry instead of combining existing flags. See example
+ /// MO_GOT_TPREL_PCREL_FLAG.
/// On a symbol operand "FOO", this indicates that the reference is actually
/// to "FOO at plt". This is used for calls and jumps to external functions
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index fcbd7f3256f867c..4b551bc51c4f0e1 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -816,9 +816,10 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// For TLS initial-exec and local-exec accesses on AIX, we have one TOC
// entry for the symbol (with the variable offset), which is differentiated
// by MO_TPREL_FLAG.
- if (MO.getTargetFlags() == PPCII::MO_TPREL_FLAG ||
- MO.getTargetFlags() == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
- MO.getTargetFlags() == PPCII::MO_TPREL_PCREL_FLAG) {
+ unsigned Flag = MO.getTargetFlags();
+ if (Flag == PPCII::MO_TPREL_FLAG ||
+ Flag == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ Flag == PPCII::MO_TPREL_PCREL_FLAG) {
assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
if (Model == TLSModel::LocalExec)
@@ -830,10 +831,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// For GD TLS access on AIX, we have two TOC entries for the symbol (one for
// the variable offset and the other for the region handle). They are
// differentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
- if (MO.getTargetFlags() == PPCII::MO_TLSGDM_FLAG)
+ if (Flag == PPCII::MO_TLSGDM_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
- if (MO.getTargetFlags() == PPCII::MO_TLSGD_FLAG ||
- MO.getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
+ if (Flag == PPCII::MO_TLSGD_FLAG || Flag == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
return MCSymbolRefExpr::VariantKind::VK_None;
};
@@ -1527,10 +1527,10 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
// The faster non-TOC-based local-exec sequence is represented by `addi`
// with an immediate operand having the MO_TPREL_FLAG. Such an instruction
// does not otherwise arise.
- const MachineOperand &MO = MI->getOperand(2);
- if (MO.getTargetFlags() == PPCII::MO_TPREL_FLAG ||
- MO.getTargetFlags() == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
- MO.getTargetFlags() == PPCII::MO_TPREL_PCREL_FLAG) {
+ unsigned Flag = MI->getOperand(2).getTargetFlags();
+ if (Flag == PPCII::MO_TPREL_FLAG ||
+ Flag == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
+ Flag == PPCII::MO_TPREL_PCREL_FLAG) {
assert(
Subtarget->hasAIXSmallLocalExecTLS() &&
"addi with thread-pointer only expected with local-exec small TLS");
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