[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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michaelmaitland wrote:

Should we remove this test from the commit?

https://github.com/llvm/llvm-project/pull/71400