[llvm] 679cc16 - [RISCV] Disable early promotion for Zbs in performANDCombine with riscv-experimental-rv64-legal-i32

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-09T09:51:31-08:00
New Revision: 679cc16c99c74c485233febb8d5b77ec4a8f0290

URL: https://github.com/llvm/llvm-project/commit/679cc16c99c74c485233febb8d5b77ec4a8f0290
DIFF: https://github.com/llvm/llvm-project/commit/679cc16c99c74c485233febb8d5b77ec4a8f0290.diff

LOG: [RISCV] Disable early promotion for Zbs in performANDCombine with riscv-experimental-rv64-legal-i32

We can match this directly in isel with the i32 type being legal.

The generic DAG combine will unpromote part of the pattern and
prevent it from being matched in isel.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 023a70d56294ad6..86ce89508ade8e3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12269,7 +12269,7 @@ static SDValue performANDCombine(SDNode *N,
   // shift amounts larger than 31 would produce poison. If we wait until
   // type legalization, we'll create RISCVISD::SRLW and we can't recover it
   // to use a BEXT instruction.
-  if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
+  if (!RV64LegalI32 && Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
       N->getValueType(0) == MVT::i32 && isOneConstant(N->getOperand(1)) &&
       N0.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.hasOneUse()) {

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
index 03b5f902c1c2158..959747e75f8c504 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
@@ -333,8 +333,7 @@ define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64ZBS-LABEL: bext_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    andi a1, a1, 31
-; RV64ZBS-NEXT:    srl a0, a0, a1
-; RV64ZBS-NEXT:    andi a0, a0, 1
+; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
   %and = and i32 %b, 31
   %shr = lshr i32 %a, %and
@@ -351,8 +350,7 @@ define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBS-LABEL: bext_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    srl a0, a0, a1
-; RV64ZBS-NEXT:    andi a0, a0, 1
+; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i32 %a, %b
   %and1 = and i32 %shr, 1