[llvm] [BOLT][RISCV] Implement basic instrumentation (PR #71664)

[Amir Ayupov via llvm-commits]

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@@ -497,6 +503,160 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
       return 2;
     return 4;
   }
+
+  InstructionListType
+  createInstrIncMemory(const MCSymbol *Target, MCContext *Ctx, bool IsLeaf,
+                       unsigned CodePointerSize) const override {
+    // We need 2 scratch registers: one for the target address (t0/x5), and one
+    // for the increment value (t1/x6).
+    // addi sp, sp, -16
+    // sd t0, 0(sp)
+    // sd t1, 8(sp)
+    // la t0, target         # 1: auipc t0, %pcrel_hi(target)
+    //                       # addi t0, t0, %pcrel_lo(1b)
+    // li t1, 1              # addi t1, zero, 1
+    // amoadd.d zero, t0, t1
+    // ld t0, 0(sp)
+    // ld t1, 8(sp)
+    // addi sp, sp, 16
+    InstructionListType Insts;
+    spillRegs(Insts, {RISCV::X5, RISCV::X6});
+
+    createLA(Insts, RISCV::X5, Target, *Ctx);
+
+    MCInst LI = MCInstBuilder(RISCV::ADDI)
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aaupov wrote:

This looks nice and readable, we need to use it more extensively.

https://github.com/llvm/llvm-project/pull/71664