[llvm] [LLVM] Make s_getpc_b64 rematerializable (PR #71823)

[via llvm-commits]

https://github.com/Acim-Maravic created https://github.com/llvm/llvm-project/pull/71823

None

>From 42f046f5f5864640d4839f3a297322f1d0884f5e Mon Sep 17 00:00:00 2001
From: Acim Maravic <acim.maravic at syrmia.com>
Date: Thu, 9 Nov 2023 17:37:12 +0100
Subject: [PATCH] [LLVM] Make s_getpc_b64 rematerializable

---
 llvm/lib/Target/AMDGPU/SOPInstructions.td |  1 +
 llvm/test/CodeGen/AMDGPU/remat-sop.mir    | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 0a16a07cb5ec35b..ffcbf48461aa531 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -292,6 +292,7 @@ def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64", [], 1>;
 def S_BITSET1_B32 : SOP1_32    <"s_bitset1_b32", [], 1>;
 def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64", [], 1>;
 
+let isReMaterializable = 1 in
 def S_GETPC_B64 : SOP1_64_0  <"s_getpc_b64",
   [(set i64:$sdst, (int_amdgcn_s_getpc))]
 >;
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index 649f0d7f7799637..f3caa1a588e32be 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -573,3 +573,25 @@ body:             |
     S_NOP 0, implicit %2
     S_ENDPGM 0
 ...
+
+---
+name:            test_remat_s_getpc_b64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: test_remat_s_getpc_b64
+    ; GCN: renamable $sgpr0_sgpr1 = S_GETPC_B64
+    ; GCN-NEXT: renamable $sgpr2_sgpr3 = S_GETPC_B64
+    ; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
+    ; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr2_sgpr3
+    ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_GETPC_B64
+    ; GCN-NEXT: S_NOP 0, implicit killed renamable $sgpr0_sgpr1
+    ; GCN-NEXT: S_ENDPGM 0
+    %0:sgpr_64 = S_GETPC_B64
+    %1:sgpr_64 = S_GETPC_B64
+    %2:sgpr_64 = S_GETPC_B64
+    S_NOP 0, implicit %0
+    S_NOP 0, implicit %1
+    S_NOP 0, implicit %2
+    S_ENDPGM 0
+...