[llvm] TableGen support for RegisterBankInfo (PR #71357)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 9 07:24:37 PST 2023
https://github.com/CBSears updated https://github.com/llvm/llvm-project/pull/71357
>From d6f25b08833463b4caa4148dee629c8e9f900a12 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 16:41:38 -0800
Subject: [PATCH 01/15] renamed emitRBIIMPL and other small changes
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 102 ++++++++++++++++++--
1 file changed, 94 insertions(+), 8 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index f851d9a79870b45..ad87c9a4d06bb30 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting a description of a target
-// register bank for a code generator.
+// register bank and register bank info for a code generator.
//
//===----------------------------------------------------------------------===//
@@ -112,7 +112,11 @@ class RegisterBankEmitter {
void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks);
void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
- std::vector<RegisterBank> &Banks);
+ const std::vector<RegisterBank> &Banks);
+ void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
+ void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
public:
RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
@@ -213,7 +217,7 @@ static void visitRegisterBankClasses(
void RegisterBankEmitter::emitBaseClassImplementation(
raw_ostream &OS, StringRef TargetName,
- std::vector<RegisterBank> &Banks) {
+ const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
const CodeGenHwModes &CGH = Target.getHwModes();
@@ -231,7 +235,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &RCs : RCsGroupedByWord) {
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
for (const auto &RC : RCs) {
- OS << " (1u << (" << RC->getQualifiedIdName() << " - "
+ std::string QualifiedRegClassID =
+ (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
+ OS << " (1u << (" << QualifiedRegClassID << " - "
<< LowestIdxInWord << ")) |\n";
}
OS << " 0,\n";
@@ -244,7 +250,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &Bank : Banks) {
std::string QualifiedBankID =
(TargetName + "::" + Bank.getEnumeratorName()).str();
- OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
+ OS << "const RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "
<< "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
<< ", /* NumRegClasses */ "
@@ -289,6 +295,76 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
+void RegisterBankEmitter::emitRBIHeader(
+ raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
+ const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+ OS << "namespace llvm {\n"
+ << "namespace " << TargetName << " {\n"
+ << "enum PartialMappingIdx {\n"
+ << " PMI_None = -1,\n";
+
+ // Banks and Register Classes are *not* emitted in their original text order
+ int ID = 0;
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ OS << " PMI_" << RC->getName() << " = " << ID++ << ",\n";
+ }
+ }
+ OS << "};\n";
+ OS << "} // end namespace " << TargetName << "\n"
+ << "} // end namespace llvm\n";
+}
+
+void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
+ const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
+ const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+ OS << "namespace llvm {\n"
+ << "namespace " << TargetName << " {\n"
+ << "RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ if (RC->RSI.isSimple()) {
+ // StartIdx is currently 0 in all of the in-tree backends
+ OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
+ << Bank.getInstanceVarName() << " },\n";
+ } else {
+ // FIXME: dumb workaround for RISCV assert() for now
+ OS << " // non-Simple() RegisterClass " << RC->getName() << "\n";
+ }
+ }
+ }
+ OS << "};\n\n";
+
+ // emit PartialMappingIdx of the first Register Class of each Register Bank
+ OS << "PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
+ for (const auto &Bank : Banks) {
+ OS << " PMI_"
+ << Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)[0]
+ ->getName()
+ << ",\n";
+ }
+ OS << "};\n\n";
+
+ // emit count of Register Classes of each Register Bank
+ OS << "int BankIDToRegisterClassCount[] = {\n";
+ for (const auto &Bank : Banks) {
+ OS << " "
+ << Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)
+ .size()
+ << ",\n";
+ }
+ OS << "};\n\n";
+
+ OS << "} // end namespace " << TargetName << "\n"
+ << "} // end namespace llvm\n";
+}
+
void RegisterBankEmitter::run(raw_ostream &OS) {
StringRef TargetName = Target.getName();
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
@@ -330,7 +406,8 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
}
Records.startTimer("Emit output");
- emitSourceFileHeader("Register Bank Source Fragments", OS);
+ emitSourceFileHeader("Register Bank And Register Bank Info Source Fragments",
+ OS);
OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
<< "#undef GET_REGBANK_DECLARATIONS\n";
emitHeader(OS, TargetName, Banks);
@@ -342,8 +419,17 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
<< "#ifdef GET_TARGET_REGBANK_IMPL\n"
<< "#undef GET_TARGET_REGBANK_IMPL\n";
emitBaseClassImplementation(OS, TargetName, Banks);
- OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
+ OS << "#endif // GET_TARGET_REGBANK_IMPL\n\n"
+ << "#ifdef GET_REGBANKINFO_DECLARATIONS\n"
+ << "#undef GET_REGBANKINFO_DECLARATIONS\n";
+ emitRBIHeader(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_DECLARATIONS\n\n"
+ << "#ifdef GET_REGBANKINFO_IMPL\n"
+ << "#undef GET_REGBANKINFO_IMPL\n";
+ emitRBIImplementation(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_IMPL\n";
}
static TableGen::Emitter::OptClass<RegisterBankEmitter>
- X("gen-register-bank", "Generate registers bank descriptions");
+ X("gen-register-bank",
+ "Generate register bank and register bank info descriptions");
>From 7bee10e30a2ba0262df3a4fde72bec533ed94f60 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 18:44:37 -0800
Subject: [PATCH 02/15] added const keyword to emitted arrays
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index ad87c9a4d06bb30..545647d8fe4cacf 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -325,7 +325,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "namespace llvm {\n"
<< "namespace " << TargetName << " {\n"
- << "RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+ << "const RegisterBankInfo::PartialMapping PartMappings[] = {\n";
for (const auto &Bank : Banks) {
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
@@ -342,7 +342,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "};\n\n";
// emit PartialMappingIdx of the first Register Class of each Register Bank
- OS << "PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
+ OS << "const PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
for (const auto &Bank : Banks) {
OS << " PMI_"
<< Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)[0]
@@ -352,7 +352,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "};\n\n";
// emit count of Register Classes of each Register Bank
- OS << "int BankIDToRegisterClassCount[] = {\n";
+ OS << "const int BankIDToRegisterClassCount[] = {\n";
for (const auto &Bank : Banks) {
OS << " "
<< Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)
>From e74d92530b75ec4d653a35dc7ec82ba96fd339f9 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 19:04:37 -0800
Subject: [PATCH 03/15] clang-format formatting
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 545647d8fe4cacf..2e0b282f324366b 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -116,7 +116,7 @@ class RegisterBankEmitter {
void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks);
void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
- const std::vector<RegisterBank> &Banks);
+ const std::vector<RegisterBank> &Banks);
public:
RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
@@ -237,8 +237,8 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &RC : RCs) {
std::string QualifiedRegClassID =
(Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
- OS << " (1u << (" << QualifiedRegClassID << " - "
- << LowestIdxInWord << ")) |\n";
+ OS << " (1u << (" << QualifiedRegClassID << " - " << LowestIdxInWord
+ << ")) |\n";
}
OS << " 0,\n";
LowestIdxInWord += 32;
@@ -318,9 +318,10 @@ void RegisterBankEmitter::emitRBIHeader(
<< "} // end namespace llvm\n";
}
-void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
- const StringRef TargetName,
- const std::vector<RegisterBank> &Banks) {
+void RegisterBankEmitter::emitRBIImplementation(
+ raw_ostream &OS,
+ const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
OS << "namespace llvm {\n"
>From 241919d4e107fab3be71406858d19967a42718cf Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 22:04:20 -0800
Subject: [PATCH 04/15] fixing clang-format complaint
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 2e0b282f324366b..37b9c0fc92d927b 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -319,8 +319,7 @@ void RegisterBankEmitter::emitRBIHeader(
}
void RegisterBankEmitter::emitRBIImplementation(
- raw_ostream &OS,
- const StringRef TargetName,
+ raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
>From 7ed514c0d01c3ed985ff3fc649e4b82730165530 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Mon, 6 Nov 2023 10:10:48 -0800
Subject: [PATCH 05/15] Updating RegisterBankEmitter.td to include CHECKs for
RegisterBankInfo tables and enum
---
llvm/test/TableGen/RegisterBankEmitter.td | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td
index 88c7ec1f7915163..901e09ddd08f75d 100644
--- a/llvm/test/TableGen/RegisterBankEmitter.td
+++ b/llvm/test/TableGen/RegisterBankEmitter.td
@@ -13,3 +13,9 @@ let Size = 32 in {
// CHECK: MyTarget::ClassARegClassID
// CHECK: MyTarget::ClassBRegClassID
def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
+
+// CHECK: enum PartialMappingIdx
+// CHECK: const RegisterBankInfo::PartialMapping PartMappings
+// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
+// CHECK: const int BankIDToRegisterClassCount
+
\ No newline at end of file
>From 1f52ef161a1558667d3e6be25eedd17b8546f76f Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Mon, 6 Nov 2023 11:21:50 -0800
Subject: [PATCH 06/15] added comment pointing at discourse RFC
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 37b9c0fc92d927b..4930d38487b4e60 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -295,6 +295,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
+// RegisterBankInfo tables and enums are discussed in https://discourse.llvm.org/t/74459
void RegisterBankEmitter::emitRBIHeader(
raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
>From ffe12e4d5f4fd2bae173c0b75bed95a0731069df Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Mon, 6 Nov 2023 12:30:25 -0800
Subject: [PATCH 07/15] Fixed clang-format complaint
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 4930d38487b4e60..cc7dd805470d0b0 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -295,7 +295,8 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
-// RegisterBankInfo tables and enums are discussed in https://discourse.llvm.org/t/74459
+// RegisterBankInfo tables and enums
+// are discussed in https://discourse.llvm.org/t/74459
void RegisterBankEmitter::emitRBIHeader(
raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
>From 1280d9c908bbdd6d8ff739a7d308f8c73addfad7 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Mon, 6 Nov 2023 14:23:37 -0800
Subject: [PATCH 08/15] added more tests to RegisterBankEmitter.td
---
llvm/test/TableGen/RegisterBankEmitter.td | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td
index 901e09ddd08f75d..a44baa648370563 100644
--- a/llvm/test/TableGen/RegisterBankEmitter.td
+++ b/llvm/test/TableGen/RegisterBankEmitter.td
@@ -15,7 +15,9 @@ let Size = 32 in {
def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
// CHECK: enum PartialMappingIdx
+// CHECK: PMI_ClassA = 0,
// CHECK: const RegisterBankInfo::PartialMapping PartMappings
+// CHECK: { 0, 32, GPRRegBank },
// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
-// CHECK: const int BankIDToRegisterClassCount
-
\ No newline at end of file
+// CHECK: PMI_ClassA,
+// CHECK: const int BankIDToRegisterClassCount
\ No newline at end of file
>From b5dc5f3f2a8118e82f2a4b15443338c2a66580a8 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Mon, 6 Nov 2023 15:04:49 -0800
Subject: [PATCH 09/15] one more RegisterBankEmitter.td test
---
llvm/test/TableGen/RegisterBankEmitter.td | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td
index a44baa648370563..65ad502cfed1c31 100644
--- a/llvm/test/TableGen/RegisterBankEmitter.td
+++ b/llvm/test/TableGen/RegisterBankEmitter.td
@@ -20,4 +20,5 @@ def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
// CHECK: { 0, 32, GPRRegBank },
// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
// CHECK: PMI_ClassA,
-// CHECK: const int BankIDToRegisterClassCount
\ No newline at end of file
+// CHECK: const int BankIDToRegisterClassCount
+// CHECK: 1,
\ No newline at end of file
>From f70194025141a71491a7d623fe4266a6a3dcd3cb Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Tue, 7 Nov 2023 15:02:03 -0800
Subject: [PATCH 10/15] the emitter now writes #error lines if it detects
either a non-Simple or untyped RegisterClass
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index cc7dd805470d0b0..f7424be639f34e1 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -332,12 +332,15 @@ void RegisterBankEmitter::emitRBIImplementation(
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
if (RC->RSI.isSimple()) {
- // StartIdx is currently 0 in all of the in-tree backends
- OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
- << Bank.getInstanceVarName() << " },\n";
+ if (RC->getValueTypes()[0].getSimple() != MVT::Untyped) {
+ // StartIdx is currently 0 in all of the in-tree backends
+ OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
+ << Bank.getInstanceVarName() << " },\n";
+ } else {
+ OS << " #error Untyped RegisterClass " << RC->getName() << "\n";
+ }
} else {
- // FIXME: dumb workaround for RISCV assert() for now
- OS << " // non-Simple() RegisterClass " << RC->getName() << "\n";
+ OS << " #error non-Simple() RegisterClass " << RC->getName() << "\n";
}
}
}
>From 6141ee2b17a67ffbdfebad358bb92b03aebc3515 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Wed, 8 Nov 2023 08:17:32 -0800
Subject: [PATCH 11/15] resolving PR comments
---
llvm/test/TableGen/RegisterBankEmitter.td | 3 +-
llvm/utils/TableGen/RegisterBankEmitter.cpp | 48 ++++++++++++---------
2 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td
index 65ad502cfed1c31..365c8879c0b9c64 100644
--- a/llvm/test/TableGen/RegisterBankEmitter.td
+++ b/llvm/test/TableGen/RegisterBankEmitter.td
@@ -21,4 +21,5 @@ def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
// CHECK: PMI_ClassA,
// CHECK: const int BankIDToRegisterClassCount
-// CHECK: 1,
\ No newline at end of file
+// CHECK: 1,
+
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index f7424be639f34e1..e5d12ccd6182098 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -107,15 +107,15 @@ class RegisterBankEmitter {
CodeGenTarget Target;
RecordKeeper &Records;
- void emitHeader(raw_ostream &OS, const StringRef TargetName,
+ void emitHeader(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
- void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
+ void emitBaseClassDefinition(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
- void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
+ void emitBaseClassImplementation(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
- void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
+ void emitRBIHeader(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
- void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
+ void emitRBIImplementation(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
public:
@@ -129,7 +129,7 @@ class RegisterBankEmitter {
/// Emit code to declare the ID enumeration and external global instance
/// variables.
void RegisterBankEmitter::emitHeader(raw_ostream &OS,
- const StringRef TargetName,
+ StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
// <Target>RegisterBankInfo.h
OS << "namespace llvm {\n"
@@ -148,7 +148,7 @@ void RegisterBankEmitter::emitHeader(raw_ostream &OS,
/// Emit declarations of the <Target>GenRegisterBankInfo class.
void RegisterBankEmitter::emitBaseClassDefinition(
- raw_ostream &OS, const StringRef TargetName,
+ raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
OS << "private:\n"
<< " static const RegisterBank *RegBanks[];\n"
@@ -295,10 +295,20 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
-// RegisterBankInfo tables and enums
-// are discussed in https://discourse.llvm.org/t/74459
+// TableGen already had some RegisterBankInfo support:
+// TargetGenRegisterBankInfo(), RegBankIDs enum, RegBanks and Sizes.
+// This emitter adds support for PartMappings, PartialMappingIdx
+// and BankIDToCopyMapIdx.
+//
+// The original implementation was supposed to infer RegisterClasses.
+// But since that wasn't finished, backends instead embedded hand crafted
+// tables and enums. This emitter generates them from .td files
+// but requires that the .td files fully describe their RegisterBanks.
+// This still doesn't support ValMappings and ValueMappingIdx.
+//
+// This was discussed in https://discourse.llvm.org/t/74459
void RegisterBankEmitter::emitRBIHeader(
- raw_ostream &OS, const StringRef TargetName,
+ raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
@@ -321,7 +331,7 @@ void RegisterBankEmitter::emitRBIHeader(
}
void RegisterBankEmitter::emitRBIImplementation(
- raw_ostream &OS, const StringRef TargetName,
+ raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
@@ -331,16 +341,14 @@ void RegisterBankEmitter::emitRBIImplementation(
for (const auto &Bank : Banks) {
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
- if (RC->RSI.isSimple()) {
- if (RC->getValueTypes()[0].getSimple() != MVT::Untyped) {
- // StartIdx is currently 0 in all of the in-tree backends
- OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
- << Bank.getInstanceVarName() << " },\n";
- } else {
- OS << " #error Untyped RegisterClass " << RC->getName() << "\n";
- }
- } else {
+ if (!RC->RSI.isSimple()) {
OS << " #error non-Simple() RegisterClass " << RC->getName() << "\n";
+ } else if (RC->getValueTypes()[0].getSimple() == MVT::Untyped) {
+ OS << " #error Untyped RegisterClass " << RC->getName() << "\n";
+ } else {
+ // StartIdx is currently 0 in all of the in-tree backends
+ OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
+ << Bank.getInstanceVarName() << " },\n";
}
}
}
>From 775e71e1fd6ccfb0c2fd2d7c7cd04c54df7c959b Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Wed, 8 Nov 2023 14:30:41 -0800
Subject: [PATCH 12/15] Added support for ValueMappings
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 93 +++++++++++++++++----
1 file changed, 77 insertions(+), 16 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index e5d12ccd6182098..b3e58b3abe1a22c 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -46,7 +46,9 @@ class RegisterBank {
/// Get the human-readable name for the bank.
StringRef getName() const { return TheDef.getValueAsString("Name"); }
/// Get the name of the enumerator in the ID enumeration.
- std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
+ std::string getEnumeratorName() const {
+ return (TheDef.getName() + "ID").str();
+ }
/// Get the name of the array holding the register class coverage data;
std::string getCoverageArrayName() const {
@@ -115,8 +117,10 @@ class RegisterBankEmitter {
const std::vector<RegisterBank> &Banks);
void emitRBIHeader(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks);
- void emitRBIImplementation(raw_ostream &OS, StringRef TargetName,
- const std::vector<RegisterBank> &Banks);
+ void emitRBIPartialMappings(raw_ostream &OS, StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
+ void emitRBIValueMappings(raw_ostream &OS, StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
public:
RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
@@ -128,8 +132,7 @@ class RegisterBankEmitter {
/// Emit code to declare the ID enumeration and external global instance
/// variables.
-void RegisterBankEmitter::emitHeader(raw_ostream &OS,
- StringRef TargetName,
+void RegisterBankEmitter::emitHeader(raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
// <Target>RegisterBankInfo.h
OS << "namespace llvm {\n"
@@ -233,10 +236,12 @@ void RegisterBankEmitter::emitBaseClassImplementation(
OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
unsigned LowestIdxInWord = 0;
for (const auto &RCs : RCsGroupedByWord) {
- OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
+ OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)
+ << "\n";
for (const auto &RC : RCs) {
std::string QualifiedRegClassID =
- (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
+ (Twine(RC->Namespace) + "::" + RC->getName()
+ + "RegClassID").str();
OS << " (1u << (" << QualifiedRegClassID << " - " << LowestIdxInWord
<< ")) |\n";
}
@@ -297,14 +302,16 @@ void RegisterBankEmitter::emitBaseClassImplementation(
// TableGen already had some RegisterBankInfo support:
// TargetGenRegisterBankInfo(), RegBankIDs enum, RegBanks and Sizes.
-// This emitter adds support for PartMappings, PartialMappingIdx
+// This emitter adds support for PartialMappings, PartialMappingIdx
// and BankIDToCopyMapIdx.
-//
+//
// The original implementation was supposed to infer RegisterClasses.
// But since that wasn't finished, backends instead embedded hand crafted
// tables and enums. This emitter generates them from .td files
// but requires that the .td files fully describe their RegisterBanks.
-// This still doesn't support ValMappings and ValueMappingIdx.
+//
+// These tables and enums are enabled by GET_REGBANKINFO_DECLARATIONS,
+// GET_REGBANKINFO_PARTIALMAPPINGS and GET_REGBANKINFO_VALUEMAPPINGS
//
// This was discussed in https://discourse.llvm.org/t/74459
void RegisterBankEmitter::emitRBIHeader(
@@ -330,14 +337,14 @@ void RegisterBankEmitter::emitRBIHeader(
<< "} // end namespace llvm\n";
}
-void RegisterBankEmitter::emitRBIImplementation(
+void RegisterBankEmitter::emitRBIPartialMappings(
raw_ostream &OS, StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
OS << "namespace llvm {\n"
<< "namespace " << TargetName << " {\n"
- << "const RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+ << "const RegisterBankInfo::PartialMapping PartialMappings[] = {\n";
for (const auto &Bank : Banks) {
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
@@ -378,6 +385,56 @@ void RegisterBankEmitter::emitRBIImplementation(
<< "} // end namespace llvm\n";
}
+// This supports ValueMappings for the simple cases.
+// For the complex cases, GET_REGBANKINFO_VALUEMAPPINGS should be left
+// undefined and the ValueMapping tables and enums must be hand crafted.
+void RegisterBankEmitter::emitRBIValueMappings(
+ raw_ostream &OS, StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
+ const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+ OS << "namespace llvm {\n"
+ << "namespace " << TargetName << " {\n"
+ << "const RegisterBankInfo::ValueMapping ValueMappings[] = {\n"
+ << " { nullptr, 0 },\n";
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ if (!RC->RSI.isSimple()) {
+ OS << " #error non-Simple() RegisterClass " << RC->getName() << "\n";
+ } else if (RC->getValueTypes()[0].getSimple() == MVT::Untyped) {
+ OS << " #error Untyped RegisterClass " << RC->getName() << "\n";
+ } else {
+ OS << " { &PartialMappings[PMI_" << RC->getName() << "], 1},\n"
+ << " { &PartialMappings[PMI_" << RC->getName() << "], 1},\n"
+ << " { &PartialMappings[PMI_" << RC->getName() << "], 1},\n";
+ }
+ }
+ }
+ OS << "};\n\n";
+
+ OS << "enum ValueMappingIdx = {\n"
+ << " VMI_Invalid = 0,\n";
+ int Offset = 1;
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ if (!RC->RSI.isSimple()) {
+ OS << " #error non-Simple() RegisterClass " << RC->getName() << "\n";
+ } else if (RC->getValueTypes()[0].getSimple() == MVT::Untyped) {
+ OS << " #error Untyped RegisterClass " << RC->getName() << "\n";
+ } else {
+ OS << " VMI_" << RC->getName() << " = " << Offset << ",\n";
+ Offset += 3;
+ }
+ }
+ }
+ OS << "};\n\n";
+
+ OS << "} // end namespace " << TargetName << "\n"
+ << "} // end namespace llvm\n";
+}
+
void RegisterBankEmitter::run(raw_ostream &OS) {
StringRef TargetName = Target.getName();
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
@@ -437,10 +494,14 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
<< "#undef GET_REGBANKINFO_DECLARATIONS\n";
emitRBIHeader(OS, TargetName, Banks);
OS << "#endif // GET_REGBANKINFO_DECLARATIONS\n\n"
- << "#ifdef GET_REGBANKINFO_IMPL\n"
- << "#undef GET_REGBANKINFO_IMPL\n";
- emitRBIImplementation(OS, TargetName, Banks);
- OS << "#endif // GET_REGBANKINFO_IMPL\n";
+ << "#ifdef GET_REGBANKINFO_PARTIALMAPPINGS\n"
+ << "#undef GET_REGBANKINFO_PARTIALMAPPINGS\n";
+ emitRBIPartialMappings(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_PARTIALMAPPINGS\n"
+ << "#ifdef GET_REGBANKINFO_VALUEMAPPINGS\n"
+ << "#undef GET_REGBANKINFO_VALUEMAPPINGS\n";
+ emitRBIValueMappings(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_VALUEMAPPINGS\n";
}
static TableGen::Emitter::OptClass<RegisterBankEmitter>
>From 18ff040a1b4a25e8a441922be167f40fe4feddc0 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Wed, 8 Nov 2023 18:24:34 -0800
Subject: [PATCH 13/15] fixed clang format complaint
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index b3e58b3abe1a22c..d0cd1eabed85ca7 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -240,8 +240,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "\n";
for (const auto &RC : RCs) {
std::string QualifiedRegClassID =
- (Twine(RC->Namespace) + "::" + RC->getName()
- + "RegClassID").str();
+ (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
OS << " (1u << (" << QualifiedRegClassID << " - " << LowestIdxInWord
<< ")) |\n";
}
>From 4250c646ebcd9350d8d683623a62b1107a68ac0e Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Wed, 8 Nov 2023 18:43:56 -0800
Subject: [PATCH 14/15] added RegisterBankEmitter test
---
llvm/test/TableGen/RegisterBankEmitter.td | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/test/TableGen/RegisterBankEmitter.td b/llvm/test/TableGen/RegisterBankEmitter.td
index 365c8879c0b9c64..18b61d4bfbdd65a 100644
--- a/llvm/test/TableGen/RegisterBankEmitter.td
+++ b/llvm/test/TableGen/RegisterBankEmitter.td
@@ -16,10 +16,16 @@ def GPRRegBank : RegisterBank<"GPR", [ClassA]>;
// CHECK: enum PartialMappingIdx
// CHECK: PMI_ClassA = 0,
-// CHECK: const RegisterBankInfo::PartialMapping PartMappings
+// CHECK: const RegisterBankInfo::PartialMapping PartialMappings
// CHECK: { 0, 32, GPRRegBank },
// CHECK: const PartialMappingIdx BankIDToFirstRegisterClassIdx
// CHECK: PMI_ClassA,
// CHECK: const int BankIDToRegisterClassCount
// CHECK: 1,
+// CHECK: const RegisterBankInfo::ValueMapping ValueMappings
+// CHECK: PMI_ClassA
+// CHECK: PMI_ClassA
+// CHECK: PMI_ClassA
+// CHECK: enum ValueMappingIdx
+// CHECK: VMI_ClassA
>From baa94ec6b67e0a348ec1075ea94873acf4f5201f Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Thu, 9 Nov 2023 07:23:54 -0800
Subject: [PATCH 15/15] Improved comment.
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index d0cd1eabed85ca7..c91a50260c2d6dc 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -299,18 +299,15 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
-// TableGen already had some RegisterBankInfo support:
-// TargetGenRegisterBankInfo(), RegBankIDs enum, RegBanks and Sizes.
-// This emitter adds support for PartialMappings, PartialMappingIdx
-// and BankIDToCopyMapIdx.
-//
-// The original implementation was supposed to infer RegisterClasses.
-// But since that wasn't finished, backends instead embedded hand crafted
-// tables and enums. This emitter generates them from .td files
-// but requires that the .td files fully describe their RegisterBanks.
+// This emitter generates PartialMappings, PartialMappingIdx,
+// BankIDToCopyMapIdx and BankIDToRegisterClassCount from the .td files.
+// However it requires that the .td files fully describe their RegisterBanks
+// and otherwise emits #error lines for the offending Registers.
//
// These tables and enums are enabled by GET_REGBANKINFO_DECLARATIONS,
// GET_REGBANKINFO_PARTIALMAPPINGS and GET_REGBANKINFO_VALUEMAPPINGS
+// So a backend which doesn't fully describe its RegisterBanks
+// will not break if it doesn't define these macros.
//
// This was discussed in https://discourse.llvm.org/t/74459
void RegisterBankEmitter::emitRBIHeader(
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