[llvm] [AArch64][GlobalISel] TableGen Selection for G_VECREDUCE_ADD (PR #70785)

[David Green via llvm-commits]

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@@ -6637,6 +6637,21 @@ def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
           ssub))>;
 }
 
+def : Pat<(i8 (vecreduce_add (v8i8 V64:$Rn))), 
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davemgreen wrote:

I think it's better to not have them separated out. It would be ideal to not have them at all, and have both SDAG and GISel share the same patterns, but sometimes it's useful to use the more natural type for the operations in the relevant ISel.

https://github.com/llvm/llvm-project/pull/70785