[llvm] [LLVM][NVPTX]Add BF16 vector instruction and fix lowering rules (PR #69415)

[Han Shen via llvm-commits]

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@@ -436,6 +436,15 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
       case ISD::FADD:
       case ISD::FMUL:
       case ISD::FSUB:
+      case ISD::SELECT:
+      case ISD::SELECT_CC:
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shenh10 wrote:

According to PTX ISA,
setp.{bf16/bf16x2} requires sm_90 or higher.
set.{u16, u32, s16, s32}.bf16, set.{u32, s32, bf16x2}.bf16x2, set.bf16.{s16,u16,f16,b16,s32,u32,f32,b32,s64,u64,f64,b64} require sm_90 or higher.





https://github.com/llvm/llvm-project/pull/69415