[llvm] 0bd0d72 - [InstCombine] Add test for zext nneg miscompile (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-11-09T11:58:02+01:00
New Revision: 0bd0d721cd71138d0d538b0a131e013ccb27ba4b

URL: https://github.com/llvm/llvm-project/commit/0bd0d721cd71138d0d538b0a131e013ccb27ba4b
DIFF: https://github.com/llvm/llvm-project/commit/0bd0d721cd71138d0d538b0a131e013ccb27ba4b.diff

LOG: [InstCombine] Add test for zext nneg miscompile (NFC)

Exposed by https://github.com/llvm/llvm-project/pull/71534 and
reported there.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
index a3485978471dc05..61039f7f1a5d9e6 100644
--- a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
+++ b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
@@ -75,3 +75,13 @@ define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
   ret <2 x i32> %op2
 }
 
+define i24 @zext_nneg(i16 %a) {
+; CHECK-LABEL: @zext_nneg(
+; CHECK-NEXT:    [[RESIZE:%.*]] = zext nneg i16 [[A:%.*]] to i24
+; CHECK-NEXT:    ret i24 [[RESIZE]]
+;
+  %and1 = and i16 %a, 32767
+  %resize = zext nneg i16 %and1 to i24
+  %and2 = and i24 %resize, 8388607
+  ret i24 %and2
+}