[llvm] [AArch64][GlobalISel] Support udot lowering for vecreduce add (PR #70784)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 06881d222dd7dbea5d1c3bf6fc4527d60e74cb00 9cef73c17310178142aaa53df6a3e754582904a7 -- llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 497d6faf8b35..d8d13cfa60b0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -300,7 +300,7 @@ void applyExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
       std::get<2>(MatchInfo) ? AArch64::G_SDOT : AArch64::G_UDOT;
   Register Ext1SrcReg = std::get<0>(MatchInfo);
 
-  // If there is one source register, create a vector of 0s as the second 
+  // If there is one source register, create a vector of 0s as the second
   // source register
   Register Ext2SrcReg;
   if (std::get<1>(MatchInfo) == 0)
@@ -330,8 +330,7 @@ void applyExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
     auto Dot = Builder.buildInstr(DotOpcode, {MidTy},
                                   {Zeroes, Ext1SrcReg, Ext2SrcReg});
     Builder.buildVecReduceAdd(MI.getOperand(0), Dot->getOperand(0));
-  } 
-  else {
+  } else {
     // If not pad the last v8 element with 0s to a v16
     SmallVector<Register, 4> Ext1UnmergeReg;
     SmallVector<Register, 4> Ext2UnmergeReg;
@@ -375,8 +374,7 @@ void applyExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
                 ->getOperand(0)
                 .getReg());
       }
-    }
-    else {
+    } else {
       // Unmerge the source vectors to v16i8
       MachineInstr *Ext1Unmerge =
           Builder.buildUnmerge(LLT::fixed_vector(16, 8), Ext1SrcReg);

``````````

</details>


https://github.com/llvm/llvm-project/pull/70784