[llvm] [AMDGPU] Add option to pre-allocate SGPR spill VGPRs (PR #70626)

[Christudasan Devadasan via llvm-commits]

cdevadas wrote:

> `SILowerSGPRSpills::extendWWMVirtRegLiveness()` no longer helps correctness when wwm register is either spilled or its live-range was split. So, can we teach RA to neither spill virtual WWM registers nor split its live-range?

That might not help. I observed for some HPCs and instrumented (asan enabled) code, the number of SGPR spills is quite large eventually requiring more virtual VGPRs while lowering them in SILowerSGPRSpills. These virtual VGPRs are of large live-ranges and often get allocated only after live-range split as their original live-ranges somehow ended up with RegMask interferences with PhysRegs (with the default 64 MaxNumVGPRs available during regalloc). Allocation happens only after splitting them into smaller live-ranges. So, I believe we can't avoid liverange split and spill for wwm-allocation.

https://github.com/llvm/llvm-project/pull/70626