[llvm] [llvm] Adding scalarization of `llvm.vector.insert` (PR #71614)

[via llvm-commits]

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@@ -5891,8 +5910,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
     InOp1 = GetWidenedVector(InOp1);
     InOp2 = GetWidenedVector(InOp2);
   } else {
-    InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
-    InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
+    do {
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qcolombet wrote:

> The widening is only really intended to apply to integer types. A `v1i1 setcc v1f16` having been turned into a `v1i16 setcc v1f16` would be better to scalarize from there if we can tell it that.

Yes, but that's not what the AArch64 lowering wants (see https://github.com/llvm/llvm-project/blob/f0cdf4b468f6ee48b0d0d51ce78145455e2f07a6/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L24550).
I believe the rational is `v1i16` is not natively supported so we widen to the larger supported vector size.
Changing that would fix this particular issue, but I believe it would create worse code in a bunch of cases.

https://github.com/llvm/llvm-project/pull/71614