[llvm] e3c120a - [RISCV] Add a Zbb+Zbs command line to rv*zbs.ll to get coverage on an existing isel pattern. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 8 22:32:05 PST 2023
Author: Craig Topper
Date: 2023-11-08T22:31:49-08:00
New Revision: e3c120a585d2740bd1a4de23112fccd82013adbc
URL: https://github.com/llvm/llvm-project/commit/e3c120a585d2740bd1a4de23112fccd82013adbc
DIFF: https://github.com/llvm/llvm-project/commit/e3c120a585d2740bd1a4de23112fccd82013adbc.diff
LOG: [RISCV] Add a Zbb+Zbs command line to rv*zbs.ll to get coverage on an existing isel pattern. NFC
This pattern wasn't tested
def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
(BCLR GPR:$rs1, GPR:$rs2)>;1
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbs.ll
llvm/test/CodeGen/RISCV/rv64zbs.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index c53e9dbfcdbf303..460d15991788238 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -2,7 +2,9 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBS
+; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBS,RV32ZBSNOZBB
+; RUN: llc -mtriple=riscv32 -mattr=+zbs,+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBS,RV32ZBSZBB
define i32 @bclr_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: bclr_i32:
@@ -62,22 +64,37 @@ define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: ret
;
-; RV32ZBS-LABEL: bclr_i64:
-; RV32ZBS: # %bb.0:
-; RV32ZBS-NEXT: andi a3, a2, 63
-; RV32ZBS-NEXT: addi a4, a3, -32
-; RV32ZBS-NEXT: slti a4, a4, 0
-; RV32ZBS-NEXT: neg a5, a4
-; RV32ZBS-NEXT: bset a2, zero, a2
-; RV32ZBS-NEXT: and a2, a5, a2
-; RV32ZBS-NEXT: bset a3, zero, a3
-; RV32ZBS-NEXT: addi a4, a4, -1
-; RV32ZBS-NEXT: and a3, a4, a3
-; RV32ZBS-NEXT: not a3, a3
-; RV32ZBS-NEXT: not a2, a2
-; RV32ZBS-NEXT: and a0, a2, a0
-; RV32ZBS-NEXT: and a1, a3, a1
-; RV32ZBS-NEXT: ret
+; RV32ZBSNOZBB-LABEL: bclr_i64:
+; RV32ZBSNOZBB: # %bb.0:
+; RV32ZBSNOZBB-NEXT: andi a3, a2, 63
+; RV32ZBSNOZBB-NEXT: addi a4, a3, -32
+; RV32ZBSNOZBB-NEXT: slti a4, a4, 0
+; RV32ZBSNOZBB-NEXT: neg a5, a4
+; RV32ZBSNOZBB-NEXT: bset a2, zero, a2
+; RV32ZBSNOZBB-NEXT: and a2, a5, a2
+; RV32ZBSNOZBB-NEXT: bset a3, zero, a3
+; RV32ZBSNOZBB-NEXT: addi a4, a4, -1
+; RV32ZBSNOZBB-NEXT: and a3, a4, a3
+; RV32ZBSNOZBB-NEXT: not a3, a3
+; RV32ZBSNOZBB-NEXT: not a2, a2
+; RV32ZBSNOZBB-NEXT: and a0, a2, a0
+; RV32ZBSNOZBB-NEXT: and a1, a3, a1
+; RV32ZBSNOZBB-NEXT: ret
+;
+; RV32ZBSZBB-LABEL: bclr_i64:
+; RV32ZBSZBB: # %bb.0:
+; RV32ZBSZBB-NEXT: andi a3, a2, 63
+; RV32ZBSZBB-NEXT: bset a4, zero, a3
+; RV32ZBSZBB-NEXT: addi a3, a3, -32
+; RV32ZBSZBB-NEXT: slti a3, a3, 0
+; RV32ZBSZBB-NEXT: addi a5, a3, -1
+; RV32ZBSZBB-NEXT: and a4, a5, a4
+; RV32ZBSZBB-NEXT: neg a3, a3
+; RV32ZBSZBB-NEXT: bset a2, zero, a2
+; RV32ZBSZBB-NEXT: and a2, a3, a2
+; RV32ZBSZBB-NEXT: andn a0, a0, a2
+; RV32ZBSZBB-NEXT: andn a1, a1, a4
+; RV32ZBSZBB-NEXT: ret
%and = and i64 %b, 63
%shl = shl nuw i64 1, %and
%neg = xor i64 %shl, -1
diff --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll
index ba43a304e6a39b9..b30b3c15196076b 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -3,6 +3,8 @@
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS
+; RUN: llc -mtriple=riscv64 -mattr=+zbs,+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS
define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32:
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