[llvm] [RISCV][GlobalISel] Vector Extension vadd Legalizer (PR #71400)

[Jiahan Xie via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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jiahanxie353 wrote:

> I think you can put a copy of each test case in each file:

sounds good!

This is irrelevant to my test cases, but is it even possible to pass `i7`, like in [here](https://github.com/llvm/llvm-project/blob/5aa934e2af8727852dec0ec1cfa0cba05d858f70/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir#L5)? 

https://github.com/llvm/llvm-project/pull/71400