[llvm] 34f83e8 - [InstSimplify] Precommit extra tests for PR71528

[Graham Hunter via llvm-commits]

Author: Graham Hunter
Date: 2023-11-08T17:02:10Z
New Revision: 34f83e86b4b70427969439683360a819a13e6f49

URL: https://github.com/llvm/llvm-project/commit/34f83e86b4b70427969439683360a819a13e6f49
DIFF: https://github.com/llvm/llvm-project/commit/34f83e86b4b70427969439683360a819a13e6f49.diff

LOG: [InstSimplify] Precommit extra tests for PR71528

Added: 
    

Modified: 
    llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll b/llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll
index bbfb072e3dcbf60..7eb8fd1c76bb087 100644
--- a/llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll
+++ b/llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+; RUN: opt -passes=instsimplify -S < %s | FileCheck %s
 
 ;; The and X, (add Y, -1) pattern is from an earlier instcombine pass which
 ;; converted
@@ -29,25 +29,65 @@
 ;; calls were the same Value*, but since there's two of them it doesn't
 ;; work and we convert the urem to add/and. CSE then gets rid of the extra
 ;; vscale, leaving us with a new pattern to match. This only works because
-;; vscale is known to be a nonzero power of 2 (assuming there's a defined
-;; range for it).
+;; vscale is known to be a power of 2 (assuming there's a defined range for it).
 
 define i64 @f1() #0 {
 ; CHECK-LABEL: define i64 @f1
 ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 4
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i64 [[TMP0]], 3
-; CHECK-NEXT:    [[TMP3:%.*]] = add nsw i64 [[TMP2]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i64 [[TMP0]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = shl i64 [[TMP0]], 3
+; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], -1
 ; CHECK-NEXT:    [[REM:%.*]] = and i64 [[TMP1]], [[TMP3]]
 ; CHECK-NEXT:    ret i64 [[REM]]
 ;
 entry:
   %0 = call i64 @llvm.vscale.i64()
-  %1 = shl nuw nsw i64 %0, 4
-  %2 = shl nuw nsw i64 %0, 3
-  %3 = add nsw i64 %2, -1
+  %1 = shl i64 %0, 4
+  %2 = shl i64 %0, 3
+  %3 = add i64 %2, -1
+  %rem = and i64 %1, %3
+  ret i64 %rem
+}
+
+;; Make sure it works if the value could also be zero.
+define i64 @test_pow2_or_zero(i64 %arg) {
+; CHECK-LABEL: define i64 @test_pow2_or_zero
+; CHECK-SAME: (i64 [[ARG:%.*]]) {
+; CHECK-NEXT:    [[NEG:%.*]] = sub i64 0, [[ARG]]
+; CHECK-NEXT:    [[X:%.*]] = and i64 [[NEG]], [[ARG]]
+; CHECK-NEXT:    [[SHL1:%.*]] = shl i64 [[X]], 4
+; CHECK-NEXT:    [[SHL2:%.*]] = shl i64 [[X]], 3
+; CHECK-NEXT:    [[MASK:%.*]] = add i64 [[SHL2]], -1
+; CHECK-NEXT:    [[REM:%.*]] = and i64 [[SHL1]], [[MASK]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+  %neg = sub i64 0, %arg
+  %x = and i64 %neg, %arg
+  %shl1 = shl i64 %x, 4
+  %shl2 = shl i64 %x, 3
+  %mask = add i64 %shl2, -1
+  %rem = and i64 %shl1, %mask
+  ret i64 %rem
+}
+
+;; Make sure it doesn't work if the value isn't known to be a power of 2.
+define i64 @no_pow2() {
+; CHECK-LABEL: define i64 @no_pow2() {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i64 [[TMP0]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = shl i64 [[TMP0]], 3
+; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], -1
+; CHECK-NEXT:    [[REM:%.*]] = and i64 [[TMP1]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+entry:
+  %0 = call i64 @llvm.vscale.i64()
+  %1 = shl i64 %0, 4
+  %2 = shl i64 %0, 3
+  %3 = add i64 %2, -1
   %rem = and i64 %1, %3
   ret i64 %rem
 }