[llvm] [AArch64][SME] Shuffle lowering, assume that the minimal SVE register is 128-bit, when NOEN is not available. (PR #71647)

[Sam Tebbs via llvm-commits]

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@@ -25889,9 +25892,8 @@ static SDValue GenerateFixedLengthSVETBL(SDValue Op, SDValue Op1, SDValue Op2,
   unsigned ElementsPerVectorReg = VTOp1.getVectorNumElements();
   unsigned MaskSize = ShuffleMask.size();
   uint64_t MaxOffset = APInt(BitsPerElt, -1, false).getZExtValue();
-  assert(ElementsPerVectorReg <= IndexLen && MaskSize <= IndexLen &&
+  assert(ElementsPerVectorReg <= IndexLen && ShuffleMask.size() <= IndexLen &&
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SamTebbs33 wrote:

Why can `MaskSize` not be used here?

https://github.com/llvm/llvm-project/pull/71647