[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Piyou Chen via llvm-commits]

BeMg wrote:

Thanks for reviewing. 

> As discussed at the dev meeting, I think this is the right overall direction.
> 
> In terms of staging, I think it makes sense to first split regalloc in it's own review, and then add the vsetvli variant between them.

Sure.

> 
> I'm concerned by the regressions you mentioned. Have you investigated them? In particular, are there any that are cause by splitting RA on it's own? If they're "only" vsetvli regressions, those are likely less scary and a bit easier to fix.

I push the some commits to represent how many llvm regression will be affect when we enable the splitting RA only, splitting RA with new vsetvl insertion pass and new vsetvl insertion pass only. In summary, Splitting RA itself doesn't change a lot but with new vsetvl insertion change a lot even only itself.

https://github.com/llvm/llvm-project/pull/70549