[llvm] [llvm] Adding scalarization of `llvm.vector.insert` (PR #71614)

[via llvm-commits]

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@@ -5891,8 +5910,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
     InOp1 = GetWidenedVector(InOp1);
     InOp2 = GetWidenedVector(InOp2);
   } else {
-    InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
-    InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
+    do {
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qcolombet wrote:

@arsenm 

For having looked at this with Rob, the problem we are facing here is:
- The legalization strategy looks like this:
  - `v1i16` is marked as `widen` by AArch64 backend and the target type is `v4i16`
  - `v1f16` is marked as `scalarize` and the target type is `f16`
So the legalization strategies don't match and we end up in this block.
Now, the problem is a single call to `WidenVector` will push `v1f16` to `v2f16` and not the expected `v4f16` and the assert line 5900 (of the old code) would break.

There may be a better way to fix that but the newly legalized operations won't get a chance to be re-legalized.

Open to suggestions, admittedly I went with a quick fix here.

FWIW, GISel doesn't have this issue.

https://github.com/llvm/llvm-project/pull/71614