[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Matt Arsenault via llvm-commits]

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@@ -2256,7 +2256,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
           }
 
           // Make sure the register fits into its register bank if any.
-          if (RegBank && Ty.isValid() &&
+          if (RegBank && Ty.isValid() && !(Ty.isVector() && Ty.isScalable()) &&
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arsenm wrote:

Does LLT need an isScalableVector and isFixedVector helper?

https://github.com/llvm/llvm-project/pull/71541