[llvm] d199fd7 - [NFC] Add f128 frexp intrinsics for PowerPC

[Qiu Chaofan via llvm-commits]

Author: Qiu Chaofan
Date: 2023-11-08T11:27:40+08:00
New Revision: d199fd76f7b76d902d8ef210d82689f299934793

URL: https://github.com/llvm/llvm-project/commit/d199fd76f7b76d902d8ef210d82689f299934793
DIFF: https://github.com/llvm/llvm-project/commit/d199fd76f7b76d902d8ef210d82689f299934793.diff

LOG: [NFC] Add f128 frexp intrinsics for PowerPC

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/f128-arith.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index 98e114f101bdf42..829db926b1704b0 100644
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -1306,3 +1306,58 @@ entry:
   ret void
 }
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128)
+
+define dso_local fp128 @qpFREXP(ptr %a, ptr %b) {
+; CHECK-LABEL: qpFREXP:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    std r0, 80(r1)
+; CHECK-NEXT:    addi r5, r1, 44
+; CHECK-NEXT:    mr r30, r4
+; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    bl frexpl
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    lwz r3, 44(r1)
+; CHECK-NEXT:    stw r3, 0(r30)
+; CHECK-NEXT:    addi r1, r1, 64
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+;
+; CHECK-P8-LABEL: qpFREXP:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    std r0, 80(r1)
+; CHECK-P8-NEXT:    addi r5, r1, 44
+; CHECK-P8-NEXT:    mr r30, r4
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v2, vs0
+; CHECK-P8-NEXT:    bl frexpl
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    lwz r3, 44(r1)
+; CHECK-P8-NEXT:    stw r3, 0(r30)
+; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
+entry:
+  %0 = load fp128, ptr %a, align 16
+  %1 = tail call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %0)
+  %2 = extractvalue { fp128, i32 } %1, 1
+  store i32 %2, ptr %b, align 4
+  %3 = extractvalue { fp128, i32 } %1, 0
+  ret fp128 %3
+}
+declare { fp128, i32 } @llvm.frexp.f128.i32(fp128)