[llvm] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 7 18:54:47 PST 2023
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@@ -0,0 +1,307 @@
+//==- RISCVSchedXiangShanNanHu.td - XiangShan-NanHu Scheduling Definitions --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-------------------------------------------------------------------------------------===//
+
+//===-------------------------------------------------------------------------------------===//
+
+// XiangShan is a high-performance open-source RISC-V processor developed by
+// the Institute of Computing Technology (ICT), Chinese Academy of Sciences.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+// XiangShan-NanHu is the second generation of XiangShan processor series.
+// Overview: https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/
+
+def XiangShanNanHuModel : SchedMachineModel {
+ let MicroOpBufferSize = 256;
+ let LoopMicroOpBufferSize = 48; // Instruction queue size
+ let IssueWidth = 6; // 6-way decode and dispatch
+ let LoadLatency = 4;
+ let MispredictPenalty = 11; // Based on estimate of pipeline depth.
+ let CompleteModel = 0;
+ let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
+ let UnsupportedFeatures = [];
----------------
wangpc-pp wrote:
Add `UnsupportedFeatures`? I don't think XiangShan has implement all extensions.
https://github.com/llvm/llvm-project/pull/70232
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