[llvm] [AMDGPU][NFC] DWARF vector composite location description operations (PR #71623)

[Tony Tye via llvm-commits]

https://github.com/t-tye created https://github.com/llvm/llvm-project/pull/71623

Summary:
Add description to AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst for "DWARF Operations to Create Vector Composite Location Descriptions" proposal to explain the main motivation is to facilitate more compact DWARF that is faster to evaluate.

Reviewers: kzhuravl, scott.linder, zoran.zaric

Subscribers:

>From 1b16d0654df4763c9a5e1d01b3a0d0dce0b796d1 Mon Sep 17 00:00:00 2001
From: Tony Tye <Tony.Tye at amd.com>
Date: Fri, 3 Nov 2023 23:43:30 +0000
Subject: [PATCH] [AMDGPU][NFC] DWARF vector composite location description
 operations

Summary:
Add description to AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
for "DWARF Operations to Create Vector Composite Location Descriptions"
proposal to explain the main motivation is to facilitate more compact
DWARF that is faster to evaluate.

Reviewers: kzhuravl, scott.linder, zoran.zaric

Subscribers:
---
 ...arfExtensionsForHeterogeneousDebugging.rst | 31 ++++++++++++++++---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
index 88e9d6131f7ddba..5dd8df231d30242 100644
--- a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
+++ b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
@@ -448,11 +448,34 @@ See ``DW_AT_LLVM_vector_size`` in :ref:`amdgpu-dwarf-base-type-entries`.
 
 AMDGPU optimized code may spill vector registers to non-global address space
 memory, and this spilling may be done only for SIMT lanes that are active on
-entry to the subprogram.
-
-To support this, a composite location description that can be created as a
-masked select is required. In addition, an operation that creates a composite
+entry to the subprogram. To support this the CFI rule for the partially spilled
+register needs to use an expression that uses the EXEC register as a bit mask to
+select between the register (for inactive lanes) and the stack spill location
+(for active lanes that are spilled). This needs to evaluate to a location
+description, and not a value, as a debugger needs to change the value if the
+user assigns to the variable.
+
+Another usage is to create an expression that evaluates to provide a vector of
+logical PCs for active and inactive lanes in a SIMT execution model. Again the
+EXEC register is used to select between active and inactive PC values. In order
+to represent a vector of PC values, a way to create a composite location
+description that is a vector of a single location is used.
+
+It may be possible to use existing DWARF to incrementally build the composite
+location description, possibly using the DWARF operations for control flow to
+create a loop. However, for the AMDGPU that would require loop iteration of 64.
+A concern is that the resulting DWARF would have a significant size and would be
+reasonably common as it is needed for every vector register that is spilled in a
+function. AMDGPU can have up to 512 vector registers. Another concern is the
+time taken to evaluate such non-trivial expressions repeatedly.
+
+To avoid these issues, a composite location description that can be created as a
+masked select is proposed. In addition, an operation that creates a composite
 location description that is a vector on another location description is needed.
+These operations generate the composite location description using a single
+DWARF operation that combines all lanes of the vector in one step. The DWARF
+expression is more compact, and can be evaluated by a consumer far more
+efficiently.
 
 An example that uses these operations is referenced in the
 :ref:`amdgpu-dwarf-further-examples` appendix.