[llvm] [AMDGPU] Add live-through register set printing to GCNRegPressurePrinter pass. (PR #71096)
Valery Pykhtin via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 7 13:20:44 PST 2023
https://github.com/vpykhtin updated https://github.com/llvm/llvm-project/pull/71096
>From ef90270217a09ea166fda9948b890aa34252d14f Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Wed, 1 Nov 2023 20:01:07 +0100
Subject: [PATCH 1/2] [AMDGPU] Add live-through register set printing to
GCNRegPressurePrinter pass.
---
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 40 +++++++++++++++++++
.../CodeGen/AMDGPU/regpressure_printer.mir | 23 +++++++++++
2 files changed, 63 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index a04c470b7b9762f..6bb2b8fccfb938b 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -496,6 +496,34 @@ char &llvm::GCNRegPressurePrinterID = GCNRegPressurePrinter::ID;
INITIALIZE_PASS(GCNRegPressurePrinter, "amdgpu-print-rp", "", true, true)
+// Return lanemask of Reg's subregs that are live-through at [Begin, End] and
+// are fully covered by Mask.
+static LaneBitmask
+getRegLiveThroughMask(const MachineRegisterInfo &MRI, const LiveIntervals &LIS,
+ Register Reg, SlotIndex Begin, SlotIndex End,
+ LaneBitmask Mask = LaneBitmask::getAll()) {
+
+ auto IsInOneSegment = [Begin, End](const LiveRange &LR) -> bool {
+ auto *Segment = LR.getSegmentContaining(Begin);
+ return Segment && Segment->contains(End);
+ };
+
+ LaneBitmask LiveThroughMask;
+ const LiveInterval &LI = LIS.getInterval(Reg);
+ if (LI.hasSubRanges()) {
+ for (auto &SR : LI.subranges()) {
+ if ((SR.LaneMask & Mask) == SR.LaneMask && IsInOneSegment(SR))
+ LiveThroughMask |= SR.LaneMask;
+ }
+ } else {
+ LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg);
+ if ((RegMask & Mask) == RegMask && IsInOneSegment(LI))
+ LiveThroughMask = RegMask;
+ }
+
+ return LiveThroughMask;
+}
+
bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
const MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
@@ -597,6 +625,18 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
if (UseDownwardTracker)
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBEndSlot, LIS, MRI));
+
+ GCNRPTracker::LiveRegSet LiveThrough;
+ for (auto [Reg, Mask] : LiveIn) {
+ LaneBitmask MaskIntersection = Mask & LiveOut.lookup(Reg);
+ if (MaskIntersection.any()) {
+ LaneBitmask LTMask = getRegLiveThroughMask(
+ MRI, LIS, Reg, MBBStartSlot, MBBEndSlot, MaskIntersection);
+ if (LTMask.any())
+ LiveThrough[Reg] = LTMask;
+ }
+ }
+ OS << PFX " Live-thr:" << llvm::print(LiveThrough, MRI);
}
OS << "...\n";
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
index d53050167e98bef..d4e2e75f383d32b 100644
--- a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
+++ b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
@@ -17,11 +17,13 @@ body: |
; RP-NEXT: 2 1 %1:sgpr_64 = IMPLICIT_DEF
; RP-NEXT: 2 1
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: Live-thr:
; RP-NEXT: bb.1:
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: SGPR VGPR
; RP-NEXT: 2 1
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: bb.2:
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: SGPR VGPR
@@ -29,6 +31,7 @@ body: |
; RP-NEXT: 2 1 S_NOP 0, implicit %0:vgpr_32, implicit %1:sgpr_64
; RP-NEXT: 0 0
; RP-NEXT: Live-out:
+ ; RP-NEXT: Live-thr:
bb.0:
%0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
%1:sgpr_64 = IMPLICIT_DEF
@@ -49,6 +52,7 @@ body: |
; RPU-NEXT: 3 0 %0:sgpr_128 = IMPLICIT_DEF
; RPU-NEXT: 3 0
; RPU-NEXT: Live-out: %0:00000000000000F3
+ ; RPU-NEXT: Live-thr:
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:00000000000000F3
; RPU-NEXT: SGPR VGPR
@@ -68,6 +72,7 @@ body: |
; RPU-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128
; RPU-NEXT: 2 0
; RPU-NEXT: Live-out: %0:00000000000000C3
+ ; RPU-NEXT: Live-thr: %0:00000000000000C0
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:00000000000000C3
; RPU-NEXT: SGPR VGPR
@@ -75,6 +80,7 @@ body: |
; RPU-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128, implicit %0.sub0:sgpr_128
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
+ ; RPU-NEXT: Live-thr:
;
; RPD-LABEL: name: live_through_test
; RPD: bb.0:
@@ -84,6 +90,7 @@ body: |
; RPD-NEXT: 4 0 %0:sgpr_128 = IMPLICIT_DEF
; RPD-NEXT: 3 0
; RPD-NEXT: Live-out: %0:00000000000000F3
+ ; RPD-NEXT: Live-thr:
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:00000000000000F3
; RPD-NEXT: SGPR VGPR
@@ -103,6 +110,7 @@ body: |
; RPD-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128
; RPD-NEXT: 2 0
; RPD-NEXT: Live-out: %0:00000000000000C3
+ ; RPD-NEXT: Live-thr: %0:00000000000000C0
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:00000000000000C3
; RPD-NEXT: SGPR VGPR
@@ -110,6 +118,7 @@ body: |
; RPD-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128, implicit %0.sub0:sgpr_128
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
+ ; RPD-NEXT: Live-thr:
bb.0:
%0:sgpr_128 = IMPLICIT_DEF
bb.1:
@@ -146,11 +155,13 @@ body: |
; RPU-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: Live-thr:
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPU-NEXT: SGPR VGPR
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:000000000000000F %1:000000000000000F
; RPU-NEXT: mis LIS: %0:0000000000000003 %1:000000000000000C
@@ -161,6 +172,7 @@ body: |
; RPU-NEXT: 0 4 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
+ ; RPU-NEXT: Live-thr:
;
; RPD-LABEL: name: upward_problem_lis_subregs_mismatch
; RPD: bb.0:
@@ -172,11 +184,13 @@ body: |
; RPD-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: Live-thr:
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: SGPR VGPR
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: SGPR VGPR
@@ -184,6 +198,7 @@ body: |
; RPD-NEXT: 0 2 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
+ ; RPD-NEXT: Live-thr:
bb.0:
undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
@@ -273,6 +288,7 @@ body: |
; RPU-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPU-NEXT: Live-thr:
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
@@ -286,11 +302,13 @@ body: |
; RPU-NEXT: DBG_VALUE
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: bb.3:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
@@ -302,6 +320,7 @@ body: |
; RPU-NEXT: 0 0 S_ENDPGM 0
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
+ ; RPU-NEXT: Live-thr:
;
; RPD-LABEL: name: only_dbg_value_sched_region
; RPD: bb.0:
@@ -376,6 +395,7 @@ body: |
; RPD-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPD-NEXT: Live-thr:
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
@@ -389,11 +409,13 @@ body: |
; RPD-NEXT: DBG_VALUE
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
+ ; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: bb.3:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
@@ -405,6 +427,7 @@ body: |
; RPD-NEXT: 0 0 S_ENDPGM 0
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
+ ; RPD-NEXT: Live-thr:
bb.0:
liveins: $vgpr0
>From bb5b639cf09e1a466ff64d73af7d10925d711333 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Tue, 7 Nov 2023 22:19:55 +0100
Subject: [PATCH 2/2] comments
---
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 1 +
.../CodeGen/AMDGPU/regpressure_printer.mir | 23 +++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 6bb2b8fccfb938b..05e510010e1356e 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -637,6 +637,7 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
}
}
OS << PFX " Live-thr:" << llvm::print(LiveThrough, MRI);
+ OS << printRP(getRegPressure(MRI, LiveThrough)) << '\n';
}
OS << "...\n";
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
index d4e2e75f383d32b..405af22d0706737 100644
--- a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
+++ b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
@@ -18,12 +18,14 @@ body: |
; RP-NEXT: 2 1
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: Live-thr:
+ ; RP-NEXT: 0 0
; RP-NEXT: bb.1:
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: SGPR VGPR
; RP-NEXT: 2 1
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: 2 1
; RP-NEXT: bb.2:
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
; RP-NEXT: SGPR VGPR
@@ -32,6 +34,7 @@ body: |
; RP-NEXT: 0 0
; RP-NEXT: Live-out:
; RP-NEXT: Live-thr:
+ ; RP-NEXT: 0 0
bb.0:
%0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
%1:sgpr_64 = IMPLICIT_DEF
@@ -53,6 +56,7 @@ body: |
; RPU-NEXT: 3 0
; RPU-NEXT: Live-out: %0:00000000000000F3
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:00000000000000F3
; RPU-NEXT: SGPR VGPR
@@ -73,6 +77,7 @@ body: |
; RPU-NEXT: 2 0
; RPU-NEXT: Live-out: %0:00000000000000C3
; RPU-NEXT: Live-thr: %0:00000000000000C0
+ ; RPU-NEXT: 1 0
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:00000000000000C3
; RPU-NEXT: SGPR VGPR
@@ -81,6 +86,7 @@ body: |
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
;
; RPD-LABEL: name: live_through_test
; RPD: bb.0:
@@ -91,6 +97,7 @@ body: |
; RPD-NEXT: 3 0
; RPD-NEXT: Live-out: %0:00000000000000F3
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:00000000000000F3
; RPD-NEXT: SGPR VGPR
@@ -111,6 +118,7 @@ body: |
; RPD-NEXT: 2 0
; RPD-NEXT: Live-out: %0:00000000000000C3
; RPD-NEXT: Live-thr: %0:00000000000000C0
+ ; RPD-NEXT: 1 0
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:00000000000000C3
; RPD-NEXT: SGPR VGPR
@@ -119,6 +127,7 @@ body: |
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
bb.0:
%0:sgpr_128 = IMPLICIT_DEF
bb.1:
@@ -156,12 +165,14 @@ body: |
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPU-NEXT: SGPR VGPR
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
; RPU-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: 0 2
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:000000000000000F %1:000000000000000F
; RPU-NEXT: mis LIS: %0:0000000000000003 %1:000000000000000C
@@ -173,6 +184,7 @@ body: |
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
;
; RPD-LABEL: name: upward_problem_lis_subregs_mismatch
; RPD: bb.0:
@@ -185,12 +197,14 @@ body: |
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: SGPR VGPR
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: 0 2
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
; RPD-NEXT: SGPR VGPR
@@ -199,6 +213,7 @@ body: |
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
bb.0:
undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
@@ -289,6 +304,7 @@ body: |
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
; RPU-NEXT: bb.1:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
@@ -303,12 +319,14 @@ body: |
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
+ ; RPU-NEXT: 0 2
; RPU-NEXT: bb.2:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
; RPU-NEXT: 0 2
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
+ ; RPU-NEXT: 0 2
; RPU-NEXT: bb.3:
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPU-NEXT: SGPR VGPR
@@ -321,6 +339,7 @@ body: |
; RPU-NEXT: 0 0
; RPU-NEXT: Live-out:
; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: 0 0
;
; RPD-LABEL: name: only_dbg_value_sched_region
; RPD: bb.0:
@@ -396,6 +415,7 @@ body: |
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
; RPD-NEXT: bb.1:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
@@ -410,12 +430,14 @@ body: |
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
+ ; RPD-NEXT: 0 2
; RPD-NEXT: bb.2:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
; RPD-NEXT: 0 2
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
+ ; RPD-NEXT: 0 2
; RPD-NEXT: bb.3:
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
; RPD-NEXT: SGPR VGPR
@@ -428,6 +450,7 @@ body: |
; RPD-NEXT: 0 0
; RPD-NEXT: Live-out:
; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: 0 0
bb.0:
liveins: $vgpr0
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