[llvm] 374fb41 - [RISCV][GISel] Add support for G_FPTOSI/G_FPTOUI with F and D extensions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 7 10:15:38 PST 2023
Author: Craig Topper
Date: 2023-11-07T10:14:37-08:00
New Revision: 374fb4126f89bcba41944a2f8089079fe34e7b57
URL: https://github.com/llvm/llvm-project/commit/374fb4126f89bcba41944a2f8089079fe34e7b57
DIFF: https://github.com/llvm/llvm-project/commit/374fb4126f89bcba41944a2f8089079fe34e7b57.diff
LOG: [RISCV][GISel] Add support for G_FPTOSI/G_FPTOUI with F and D extensions.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fptoi.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fptoi.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 8e2f99601e1ba9b..3adedf9bc2a5bd7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -217,6 +217,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
(ST.hasStdExtD() && typeIs(0, s64)(Query));
});
+ getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
+ .legalIf([=, &ST](const LegalityQuery &Query) -> bool {
+ return typeInSet(0, {s32, sXLen})(Query) &&
+ ((ST.hasStdExtF() && typeIs(1, s32)(Query)) ||
+ (ST.hasStdExtD() && typeIs(1, s64)(Query)));
+ })
+ .widenScalarToNextPow2(0)
+ .clampScalar(0, s32, sXLen);
+
getLegacyLegalizerInfo().computeTables();
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 3fc00cb760358bb..02b89b902b9924f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -205,14 +205,20 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FPEXT:
case TargetOpcode::G_FPTRUNC: {
LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
- (void)ToTy;
LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
- (void)FromTy;
OperandsMapping =
getOperandsMapping({getFPValueMapping(ToTy.getSizeInBits()),
getFPValueMapping(FromTy.getSizeInBits())});
break;
}
+ case TargetOpcode::G_FPTOSI:
+ case TargetOpcode::G_FPTOUI: {
+ LLT Ty = MRI.getType(MI.getOperand(1).getReg());
+ OperandsMapping =
+ getOperandsMapping({GPRValueMapping,
+ getFPValueMapping(Ty.getSizeInBits())});
+ break;
+ }
case TargetOpcode::G_FCONSTANT: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OperandsMapping =
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir
new file mode 100644
index 000000000000000..ab737be929ef277
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir
@@ -0,0 +1,92 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fptosi_s32_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s32) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s32) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s32) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s32) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
new file mode 100644
index 000000000000000..afa53c8de76db97
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
@@ -0,0 +1,184 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fptosi_s32_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s32) = G_FPTOSI %0(s32)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s32) = G_FPTOUI %0(s32)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_L_S:%[0-9]+]]:gpr = nofpexcept FCVT_L_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s64) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[FCVT_LU_S:%[0-9]+]]:gpr = nofpexcept FCVT_LU_S [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_S]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s32) = COPY $f10_f
+ %1:gprb(s64) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s32) = G_FPTOSI %0(s64)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s32) = G_FPTOUI %0(s64)
+ %2:gprb(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_L_D:%[0-9]+]]:gpr = nofpexcept FCVT_L_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_L_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s64) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[FCVT_LU_D:%[0-9]+]]:gpr = nofpexcept FCVT_LU_D [[COPY]], 1
+ ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_D]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s64) = COPY $f10_d
+ %1:gprb(s64) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fptoi.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fptoi.mir
new file mode 100644
index 000000000000000..d32b4350793d5b4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fptoi.mir
@@ -0,0 +1,320 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fptosi_s1_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s1_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s1) = G_FPTOSI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s1_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s1_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s1) = G_FPTOUI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s8_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s8) = G_FPTOSI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s8_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s8) = G_FPTOUI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s16_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s16) = G_FPTOSI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s16_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s16) = G_FPTOUI %0(s32)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s1_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s1_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s1) = G_FPTOSI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s1_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s1_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s1) = G_FPTOUI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s8_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s8) = G_FPTOSI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s8_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s8) = G_FPTOUI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s16_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s16) = G_FPTOSI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s16_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s16) = G_FPTOUI %0(s64)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fptoi.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fptoi.mir
new file mode 100644
index 000000000000000..f233e6279a13d01
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fptoi.mir
@@ -0,0 +1,416 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fptosi_s1_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s1_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s1) = G_FPTOSI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s1_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s1_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s1) = G_FPTOUI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s8_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s8) = G_FPTOSI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s8_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s8) = G_FPTOUI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s16_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s16) = G_FPTOSI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s16_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s16) = G_FPTOUI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOSI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOUI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s32
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s1_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s1_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s1) = G_FPTOSI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s1_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s1_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s1) = G_FPTOUI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s8_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s8_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s8) = G_FPTOSI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s8_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s8_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s8) = G_FPTOUI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s16_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s16_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s16) = G_FPTOSI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s16_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s16_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s16) = G_FPTOUI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOSI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOUI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s64
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
new file mode 100644
index 000000000000000..10fb4f6ba459665
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fptosi_s32_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
new file mode 100644
index 000000000000000..adfa458939d12ba
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fptosi_s32_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOSI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s32_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = G_FPTOUI %0(s32)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptosi_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPTOSI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_f
+
+ ; CHECK-LABEL: name: fptoui_s64_s32
+ ; CHECK: liveins: $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $f10_f
+ %1:_(s64) = G_FPTOUI %0(s32)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s32_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOSI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s32_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s32_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[FPTOUI]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s32) = G_FPTOUI %0(s64)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptosi_s64_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptosi_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FPTOSI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fptoui_s64_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_d
+
+ ; CHECK-LABEL: name: fptoui_s64_s64
+ ; CHECK: liveins: $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = G_FPTOUI %0(s64)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
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