[llvm] [RISCV][GlobalISel] Vector Extension vadd Legalizer (PR #71400)

[Jiahan Xie via llvm-commits]

jiahanxie353 wrote:

Hi all,

I have [a simple test case](https://github.com/jiahanxie353/llvm-project/blob/137e9a3e1cd39c0a9b6736110f10b2d590fb616c/legalize-vadd.mir#L6) that involve scalable vector n x 1 x 32 legalization and [get it passed/legalized](https://github.com/jiahanxie353/llvm-project/blob/137e9a3e1cd39c0a9b6736110f10b2d590fb616c/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp#L39).

If it looks good, I can move on to support different grouping number combined with different element types/lengths. Since according to the [RISCV V Extension Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#342-vector-register-grouping-vlmul20), integer `LMUL` can be 1 or 2 or 4 or 8, so I can just ad-hoc `nxv1s32`, `nxv2s32`, ..., and `nxv1s64`, `nxv2s64`, etc.

## Issue

1. It prints out `LLT_invalid` when I have `-debug` flag on when running the test. The invalid information is printed [here](https://github.com/llvm/llvm-project/blob/75d6795e420274346b14aca8b6bd49bfe6030eeb/llvm/lib/CodeGen/LowLevelType.cpp#L47). Do you have any insight? Should it be in my scope of work?

2. `LMUL` < 1 is unclear, and I came across [this dicussion](https://discourse.llvm.org/t/on-vectorization-under-risc-v-and-its-existing-interface-to-control-scalable-vectorization-width-vectorize-width-vf-scalable/66893/11).

What do you think to tackle with fractional `LMUL`?

https://github.com/llvm/llvm-project/pull/71400