[llvm] [AMDGPU] Folding imm offset in more cases for scratch access (PR #70634)

[Jay Foad via llvm-commits]

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@@ -244,7 +244,9 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
                         unsigned Size) const;
   bool isFlatScratchBaseLegal(
-      Register Base, uint64_t FlatVariant = SIInstrFlags::FlatScratch) const;
+      MachineInstr &FullAddr, MachineInstr *PartAddr = nullptr,
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jayfoad wrote:

In GlobalISel it is more normal to pass values around as `Register` instead of `MachineInstr&`. Is there a reason you changed this?

https://github.com/llvm/llvm-project/pull/70634