[llvm] [LLVM][NVPTX]Add BF16 vector instruction and fix lowering rules (PR #69415)

[Han Shen via llvm-commits]

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@@ -555,6 +555,34 @@ multiclass F2<string OpcStr, SDNode OpNode> {
                            [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
 }
 
+multiclass F2_Support_Half<string OpcStr, SDNode OpNode> {
+   def bf16 :     NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a),
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shenh10 wrote:

Done

https://github.com/llvm/llvm-project/pull/69415