[llvm] [AMDGPU] Folding imm offset in more cases for scratch access (PR #70634)

[via llvm-commits]

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@@ -1886,7 +1899,8 @@ bool AMDGPUDAGToDAGISel::SelectScratchSVAddr(SDNode *N, SDValue Addr,
     return false;
   }
 
-  if (!isFlatScratchBaseLegal(SAddr) || !isFlatScratchBaseLegal(VAddr))
+  if (!isFlatScratchBaseLegal(Addr, SAddr) ||
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petar-avramovic wrote:

Offset values in register (ADDR and SADDR) are treated as **unsigned** by hardware (I tested this and confirmed incorrect behavior when offset value in register was negative). Imm offset value is **signed**. Documentation looks correct.

https://github.com/llvm/llvm-project/pull/70634