[llvm] [AArch64] Fix tryMergeAdjacentSTG function in PrologEpilog pass (PR #68873)

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git-clang-format --diff 0ce6255a50584863c2f462390cac6a63ccb5f136 9350a2bcb510720ac7f12e8491c5ed76e2cbf181 -- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 260f89dfd260..404fcafb5046 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3772,7 +3772,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
   // the insert list, this liveness check is done (which is not needed).
   LivePhysRegs LR(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
   LR.addLiveOuts(*MBB);
-  for (auto I = MBB->rbegin(); ; ++I) {
+  for (auto I = MBB->rbegin();; ++I) {
     MachineInstr &MIns = *I;
     if (MIns == InsertI)
       break;

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https://github.com/llvm/llvm-project/pull/68873