[llvm] [RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (PR #71483)

[Yeting Kuo via llvm-commits]

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@@ -3501,6 +3501,19 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
   if (!True.isMachineOpcode())
     return false;
 
+  // This transformation is illegal for viota.m when Mask is not a true mask.
+  switch (True->getMachineOpcode()) {
+  case RISCV::PseudoVIOTA_M_MF8:
+  case RISCV::PseudoVIOTA_M_MF4:
+  case RISCV::PseudoVIOTA_M_MF2:
+  case RISCV::PseudoVIOTA_M_M1:
+  case RISCV::PseudoVIOTA_M_M2:
+  case RISCV::PseudoVIOTA_M_M4:
+  case RISCV::PseudoVIOTA_M_M8:
+    if (Mask && !usesAllOnesMask(Mask, Glue))
+      return false;
+  }
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yetingk wrote:

Thank you. I does similar refine in https://github.com/llvm/llvm-project/pull/71483/commits/540ce31776a33148da8ef6fabea09fe4a34ab2e6

https://github.com/llvm/llvm-project/pull/71483