[llvm] [RISCV][GlobalISel] Vector Extension vadd Legalizer (PR #71400)

[Jiahan Xie via llvm-commits]

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@@ -0,0 +1,9 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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jiahanxie353 wrote:

Sounds reasonable! And I tried to change it, and used `SelectionDAG` to run. But again, it fails at 
```
/llvm-project/llvm/include/llvm/CodeGen/MachineRegisterInfo.h:665: const TargetRegisterClass *llvm::MachineRegisterInfo::getRegClass(Register) const: Assertion `isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) && "Register class not set, wrong accessor"' failed.
```

Nevertheless, as you comment before:
> I touched this function in one of my PRs: https://github.com/llvm/llvm-project/pull/70881. Maybe you can investigate why we're failing this assertion as a result of this test case? Were we supposed to assign a register a regclass? Maybe we need to do some work in RegBankSelection to avoid this failure?

> I am not sure why the failure happens with the options you give it. However, I will note that SDAG works on LLVM IR, not MIR so I don't think you'd really get the result you intended on getting anyway.

Let me just proceed with `-global-isel` and see if it will fail at the same spot. If it does, I will take a closer look at it; for now, I'll just ignore `SelectionDAG`'s error since it's an MIR test and that 
> I will note that SDAG works on LLVM IR, not MIR so I don't think you'd really get the result you intended on getting anyway

What do you think

https://github.com/llvm/llvm-project/pull/71400