[llvm] [RISCV] Add bset optimization for left shift code (PR #71420)

[Craig Topper via llvm-commits]

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@@ -554,6 +554,8 @@ def : Pat<(XLenVT (and (shiftop<srl> GPR:$rs1, (XLenVT GPR:$rs2)), 1)),
 
 def : Pat<(XLenVT (shiftop<shl> 1, (XLenVT GPR:$rs2))),
           (BSET (XLenVT X0), GPR:$rs2)>;
+def : Pat<(XLenVT (xor (shiftopw<riscv_sllw> -1, (XLenVT GPR:$rs2)), -1)),
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topperc wrote:

shiftopw looks through 'and' mask on the lower 5 bits since sllw only uses 5 bits. Bset uses 6 bits on rv64. So this changes behavior.

I think RISCVISD::SLLW also calls SimplifyDemandedBits on the shift amount during DAGCombine which is also an issue.

https://github.com/llvm/llvm-project/pull/71420