[llvm] 1c6102d - [AMDGPU] Regenerate checks for long-branch-reserve-register.ll

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-11-06T15:33:23Z
New Revision: 1c6102d19b445c6d17d3792dde0fc308efebc875

URL: https://github.com/llvm/llvm-project/commit/1c6102d19b445c6d17d3792dde0fc308efebc875
DIFF: https://github.com/llvm/llvm-project/commit/1c6102d19b445c6d17d3792dde0fc308efebc875.diff

LOG: [AMDGPU] Regenerate checks for long-branch-reserve-register.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
index dc7d2eed53696e6..fd543b96b0cf36d 100644
--- a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
+++ b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
 
 ; OBJ:       Relocations [
@@ -54,32 +55,32 @@ bb3:
 define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {
 ; GCN-LABEL: uniform_conditional_min_long_forward_branch:
 ; GCN:       ; %bb.0: ; %bb0
-; GCN-NEXT:  	 s_load_dword s2, s[0:1], 0xb
-; GCN-NEXT:  	 s_waitcnt lgkmcnt(0)
-; GCN-NEXT:  	 s_cmp_eq_u32 s2, 0
-; GCN-NEXT:  	 s_cbranch_scc0 .LBB1_1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_cmp_eq_u32 s2, 0
+; GCN-NEXT:    s_cbranch_scc0 .LBB1_1
 ; GCN-NEXT:  .LBB1_3: ; %bb0
-; GCN-NEXT:  	 s_getpc_b64 s[8:9]
+; GCN-NEXT:    s_getpc_b64 s[8:9]
 ; GCN-NEXT:  .Lpost_getpc0:
-; GCN-NEXT:  	 s_add_u32 s8, s8, (.LBB1_2-.Lpost_getpc0)&4294967295
-; GCN-NEXT:  	 s_addc_u32 s9, s9, (.LBB1_2-.Lpost_getpc0)>>32
-; GCN-NEXT:  	 s_setpc_b64 s[8:9]
+; GCN-NEXT:    s_add_u32 s8, s8, (.LBB1_2-.Lpost_getpc0)&4294967295
+; GCN-NEXT:    s_addc_u32 s9, s9, (.LBB1_2-.Lpost_getpc0)>>32
+; GCN-NEXT:    s_setpc_b64 s[8:9]
 ; GCN-NEXT:  .LBB1_1: ; %bb2
-; GCN-NEXT:  	 ;;#ASMSTART
-; GCN-NEXT:  	 v_nop_e64
-; GCN-NEXT:     v_nop_e64
-; GCN-NEXT:     v_nop_e64
-; GCN-NEXT:     v_nop_e64
-; GCN-NEXT:  	 ;;#ASMEND
+; GCN-NEXT:    ;;#ASMSTART
+; GCN-NEXT:    v_nop_e64
+; GCN-NEXT:    v_nop_e64
+; GCN-NEXT:    v_nop_e64
+; GCN-NEXT:    v_nop_e64
+; GCN-NEXT:    ;;#ASMEND
 ; GCN-NEXT:  .LBB1_2: ; %bb3
-; GCN-NEXT:  	 s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:  	 s_mov_b32 s7, 0xf000
-; GCN-NEXT:  	 s_mov_b32 s6, -1
-; GCN-NEXT:  	 v_mov_b32_e32 v0, s2
-; GCN-NEXT:  	 s_waitcnt lgkmcnt(0)
-; GCN-NEXT:  	 buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT:  	 s_waitcnt vmcnt(0)
-; GCN-NEXT:  	 s_endpgm
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v0, s2
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    s_endpgm
 bb0:
   %cmp = icmp eq i32 %cnd, 0
   br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
@@ -290,7 +291,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
 ; GCN-NEXT:    v_nop_e64
 ; GCN-NEXT:    v_nop_e64
 ; GCN-NEXT:    ;;#ASMEND
-; GCN-NEXT:  s_mov_b64 vcc, exec
+; GCN-NEXT:    s_mov_b64 vcc, exec
 ; GCN-NEXT:    s_cbranch_execnz .LBB5_5
 ; GCN-NEXT:  .LBB5_9: ; %bb3
 ; GCN-NEXT:    s_getpc_b64 s[4:5]