[llvm] 8a417b7 - [X86] Fix typo in comment in X86FixupLEAs. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-05T23:04:07-08:00
New Revision: 8a417b7b7e4311a3ca41a21f9c016dfdd3e6236c

URL: https://github.com/llvm/llvm-project/commit/8a417b7b7e4311a3ca41a21f9c016dfdd3e6236c
DIFF: https://github.com/llvm/llvm-project/commit/8a417b7b7e4311a3ca41a21f9c016dfdd3e6236c.diff

LOG: [X86] Fix typo in comment in X86FixupLEAs. NFC

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86FixupLEAs.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index c702c015d7b381d..ceafbf177352a87 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -330,8 +330,8 @@ static inline bool isInefficientLEAReg(unsigned Reg) {
          Reg == X86::R13D || Reg == X86::R13;
 }
 
-/// Returns true if this LEA uses base an index registers, and the base register
-/// is known to be inefficient for the subtarget.
+/// Returns true if this LEA uses base and index registers, and the base
+/// register is known to be inefficient for the subtarget.
 // TODO: use a variant scheduling class to model the latency profile
 // of LEA instructions, and implement this logic as a scheduling predicate.
 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,