[llvm] add RegisterBankInfo support to RegisterBankEmitter (PR #70895)

[via llvm-commits]

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@@ -289,6 +293,73 @@ void RegisterBankEmitter::emitBaseClassImplementation(
      << "} // end namespace llvm\n";
 }
 
+void RegisterBankEmitter::emitRBIHeader(
+    raw_ostream &OS, const StringRef TargetName,
+    const std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "enum PartialMappingIdx {\n"
+     << "  PMI_None = -1,\n";
+
+  // Banks and Register Classes are *not* emitted in their original text order
+  int ID = 0;
+  for (const auto &Bank : Banks) {
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      OS << "  PMI_" << RC->getName() << " = " << ID++ << ",\n";
+    }
+  }
+  OS << "};\n";
+  OS << "} // end namespace " << TargetName << "\n"
+     << "} // end namespace llvm\n";
+}
+
+void RegisterBankEmitter::emitRBIIMPL(raw_ostream &OS,
+                                      const StringRef TargetName,
+                                      const std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+  // Is StartIdx RC->RSI.getSimple().SpillAlignment ?
+  // StartIdx is 0 in all of the in-tree backends
+  OS << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n"
+     << "RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+  for (const auto &Bank : Banks) {
+    for (const CodeGenRegisterClass *RC :
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+      if (RC->RSI.isSimple()) // FIXME: dumb workaround for RISCV for now
+        OS << "  { 0, " << RC->RSI.getSimple().RegSize << ", "
+           << Bank.getInstanceVarName() << " },\n";
+    }
+  }
+  OS << "};\n\n";
+
+  // emit PartialMappingIdx of the first Register Class of each Register Bank
+  OS << "PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
+  for (const auto &Bank : Banks) {
+    OS << "  PMI_"
+       << Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)[0]
+              ->getName()
+       << ",\n";
+  }
+  OS << "};\n\n";
+
+  // emit count of Register Classes of each Register Bank
+  OS << "int BankIDToRegisterClassCount[] = {\n";
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CBSears wrote:

Will do. The TableGen code is easy but I am struggling with GitHub PRs. So I may resolve the comments if I can't figure out how to update the PR and then recommit if I have to. I use git locally but I'm new to GitHub.

https://github.com/llvm/llvm-project/pull/70895