[llvm] 5d2f9ae - [RISCV][GISel] Add call preserved regmask to calls created by RISCVCallLowering::lowerCall.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 5 11:48:52 PST 2023
Author: Craig Topper
Date: 2023-11-05T11:45:35-08:00
New Revision: 5d2f9aee662fd83dc3265d75a55f3f4b4d4b79bb
URL: https://github.com/llvm/llvm-project/commit/5d2f9aee662fd83dc3265d75a55f3f4b4d4b79bb
DIFF: https://github.com/llvm/llvm-project/commit/5d2f9aee662fd83dc3265d75a55f3f4b4d4b79bb.diff
LOG: [RISCV][GISel] Add call preserved regmask to calls created by RISCVCallLowering::lowerCall.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 1806fcf4b5a1664..4b0296f60d13012 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -456,6 +456,8 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
.buildInstrNoInsert(Info.Callee.isReg() ? RISCV::PseudoCALLIndirect
: RISCV::PseudoCALL)
.add(Info.Callee);
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ Call.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
RISCVOutgoingValueAssigner ArgAssigner(
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
index 8fc77feae2d431d..a1d336c52035c86 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I,ILP32 %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I,ILP32F %s
; This file contains tests that should have identical output for the ilp32,
; and ilp32f.
@@ -31,18 +31,31 @@ define i32 @callee_double_in_regs(i32 %a, double %b) nounwind {
}
define i32 @caller_double_in_regs() nounwind {
- ; RV32I-LABEL: name: caller_double_in_regs
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
- ; RV32I-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
- ; RV32I-NEXT: $x10 = COPY [[C]](s32)
- ; RV32I-NEXT: $x11 = COPY [[UV]](s32)
- ; RV32I-NEXT: $x12 = COPY [[UV1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: $x10 = COPY [[COPY]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_double_in_regs
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; ILP32-NEXT: $x10 = COPY [[C]](s32)
+ ; ILP32-NEXT: $x11 = COPY [[UV]](s32)
+ ; ILP32-NEXT: $x12 = COPY [[UV1]](s32)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: $x10 = COPY [[COPY]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_double_in_regs
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; ILP32F-NEXT: $x10 = COPY [[C]](s32)
+ ; ILP32F-NEXT: $x11 = COPY [[UV]](s32)
+ ; ILP32F-NEXT: $x12 = COPY [[UV1]](s32)
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: $x10 = COPY [[COPY]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_double_in_regs(i32 1, double 2.0)
ret i32 %1
}
@@ -59,16 +72,27 @@ define double @callee_small_scalar_ret() nounwind {
}
define i64 @caller_small_scalar_ret() nounwind {
- ; RV32I-LABEL: name: caller_small_scalar_ret
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, implicit-def $x1, implicit-def $x10, implicit-def $x11
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; RV32I-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
- ; RV32I-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
- ; RV32I-NEXT: $x10 = COPY [[UV]](s32)
- ; RV32I-NEXT: $x11 = COPY [[UV1]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
+ ; ILP32-LABEL: name: caller_small_scalar_ret
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+ ; ILP32-NEXT: $x10 = COPY [[UV]](s32)
+ ; ILP32-NEXT: $x11 = COPY [[UV1]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10, implicit $x11
+ ;
+ ; ILP32F-LABEL: name: caller_small_scalar_ret
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32F-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+ ; ILP32F-NEXT: $x10 = COPY [[UV]](s32)
+ ; ILP32F-NEXT: $x11 = COPY [[UV1]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10, implicit $x11
%1 = call double @callee_small_scalar_ret()
%2 = bitcast double %1 to i64
ret i64 %2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index e6837b90e3bb161..0602222d72f401e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I,ILP32 %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I,ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I,ILP32D %s
; This file contains tests that should have identical output for the ilp32,
; ilp32f, and ilp32d ABIs. i.e. where no arguments are passed according to
@@ -35,18 +35,44 @@ define i32 @callee_i64_in_regs(i32 %a, i64 %b) nounwind {
}
define i32 @caller_i64_in_regs() nounwind {
- ; RV32I-LABEL: name: caller_i64_in_regs
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; RV32I-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
- ; RV32I-NEXT: $x10 = COPY [[C]](s32)
- ; RV32I-NEXT: $x11 = COPY [[UV]](s32)
- ; RV32I-NEXT: $x12 = COPY [[UV1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: $x10 = COPY [[COPY]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_i64_in_regs
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; ILP32-NEXT: $x10 = COPY [[C]](s32)
+ ; ILP32-NEXT: $x11 = COPY [[UV]](s32)
+ ; ILP32-NEXT: $x12 = COPY [[UV1]](s32)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: $x10 = COPY [[COPY]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_i64_in_regs
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; ILP32F-NEXT: $x10 = COPY [[C]](s32)
+ ; ILP32F-NEXT: $x11 = COPY [[UV]](s32)
+ ; ILP32F-NEXT: $x12 = COPY [[UV1]](s32)
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: $x10 = COPY [[COPY]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32D-LABEL: name: caller_i64_in_regs
+ ; ILP32D: bb.1 (%ir-block.0):
+ ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; ILP32D-NEXT: $x10 = COPY [[C]](s32)
+ ; ILP32D-NEXT: $x11 = COPY [[UV]](s32)
+ ; ILP32D-NEXT: $x12 = COPY [[UV1]](s32)
+ ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_i64_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
+ ; ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_i64_in_regs(i32 1, i64 2)
ret i32 %1
}
@@ -100,39 +126,107 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i
}
define i32 @caller_many_scalars() nounwind {
- ; RV32I-LABEL: name: caller_many_scalars
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
- ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
- ; RV32I-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
- ; RV32I-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
- ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s32)
- ; RV32I-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
- ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; RV32I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s32)
- ; RV32I-NEXT: G_STORE [[C7]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4)
- ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
- ; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32)
- ; RV32I-NEXT: $x12 = COPY [[C2]](s32)
- ; RV32I-NEXT: $x13 = COPY [[UV]](s32)
- ; RV32I-NEXT: $x14 = COPY [[UV1]](s32)
- ; RV32I-NEXT: $x15 = COPY [[C4]](s32)
- ; RV32I-NEXT: $x16 = COPY [[C5]](s32)
- ; RV32I-NEXT: $x17 = COPY [[UV2]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
- ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_many_scalars
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; ILP32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; ILP32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; ILP32-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; ILP32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; ILP32-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; ILP32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+ ; ILP32-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
+ ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
+ ; ILP32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; ILP32-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s32)
+ ; ILP32-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; ILP32-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s32)
+ ; ILP32-NEXT: G_STORE [[C7]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4)
+ ; ILP32-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; ILP32-NEXT: $x11 = COPY [[ANYEXT1]](s32)
+ ; ILP32-NEXT: $x12 = COPY [[C2]](s32)
+ ; ILP32-NEXT: $x13 = COPY [[UV]](s32)
+ ; ILP32-NEXT: $x14 = COPY [[UV1]](s32)
+ ; ILP32-NEXT: $x15 = COPY [[C4]](s32)
+ ; ILP32-NEXT: $x16 = COPY [[C5]](s32)
+ ; ILP32-NEXT: $x17 = COPY [[UV2]](s32)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_many_scalars
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; ILP32F-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; ILP32F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; ILP32F-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; ILP32F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; ILP32F-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+ ; ILP32F-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
+ ; ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
+ ; ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s32)
+ ; ILP32F-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; ILP32F-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; ILP32F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s32)
+ ; ILP32F-NEXT: G_STORE [[C7]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4)
+ ; ILP32F-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; ILP32F-NEXT: $x11 = COPY [[ANYEXT1]](s32)
+ ; ILP32F-NEXT: $x12 = COPY [[C2]](s32)
+ ; ILP32F-NEXT: $x13 = COPY [[UV]](s32)
+ ; ILP32F-NEXT: $x14 = COPY [[UV1]](s32)
+ ; ILP32F-NEXT: $x15 = COPY [[C4]](s32)
+ ; ILP32F-NEXT: $x16 = COPY [[C5]](s32)
+ ; ILP32F-NEXT: $x17 = COPY [[UV2]](s32)
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32D-LABEL: name: caller_many_scalars
+ ; ILP32D: bb.1 (%ir-block.0):
+ ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; ILP32D-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; ILP32D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; ILP32D-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+ ; ILP32D-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
+ ; ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
+ ; ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
+ ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s32)
+ ; ILP32D-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; ILP32D-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; ILP32D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s32)
+ ; ILP32D-NEXT: G_STORE [[C7]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4)
+ ; ILP32D-NEXT: $x10 = COPY [[ANYEXT]](s32)
+ ; ILP32D-NEXT: $x11 = COPY [[ANYEXT1]](s32)
+ ; ILP32D-NEXT: $x12 = COPY [[C2]](s32)
+ ; ILP32D-NEXT: $x13 = COPY [[UV]](s32)
+ ; ILP32D-NEXT: $x14 = COPY [[UV1]](s32)
+ ; ILP32D-NEXT: $x15 = COPY [[C4]](s32)
+ ; ILP32D-NEXT: $x16 = COPY [[C5]](s32)
+ ; ILP32D-NEXT: $x17 = COPY [[UV2]](s32)
+ ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
ret i32 %1
}
@@ -151,17 +245,41 @@ define i64 @callee_small_scalar_ret() nounwind {
}
define i32 @caller_small_scalar_ret() nounwind {
- ; RV32I-LABEL: name: caller_small_scalar_ret
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, implicit-def $x1, implicit-def $x10, implicit-def $x11
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; RV32I-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
- ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s64), [[MV]]
- ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
- ; RV32I-NEXT: $x10 = COPY [[ZEXT]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_small_scalar_ret
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; ILP32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s64), [[MV]]
+ ; ILP32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; ILP32-NEXT: $x10 = COPY [[ZEXT]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_small_scalar_ret
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32F-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; ILP32F-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s64), [[MV]]
+ ; ILP32F-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; ILP32F-NEXT: $x10 = COPY [[ZEXT]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32D-LABEL: name: caller_small_scalar_ret
+ ; ILP32D: bb.1 (%ir-block.0):
+ ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 987654321234567
+ ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; ILP32D-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s64), [[MV]]
+ ; ILP32D-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; ILP32D-NEXT: $x10 = COPY [[ZEXT]](s32)
+ ; ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i64 @callee_small_scalar_ret()
%2 = icmp eq i64 987654321234567, %1
%3 = zext i1 %2 to i32
@@ -184,15 +302,35 @@ define %struct.small @callee_small_struct_ret() nounwind {
}
define i32 @caller_small_struct_ret() nounwind {
- ; RV32I-LABEL: name: caller_small_struct_ret
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, implicit-def $x1, implicit-def $x10, implicit-def $x11
- ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RV32I-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
- ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[PTRTOINT]]
- ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_small_struct_ret
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; ILP32-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
+ ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; ILP32-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_small_struct_ret
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; ILP32F-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
+ ; ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; ILP32F-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32D-LABEL: name: caller_small_struct_ret
+ ; ILP32D: bb.1 (%ir-block.0):
+ ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; ILP32D-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
+ ; ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32D-NEXT: PseudoRET implicit $x10
%1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1
@@ -237,18 +375,44 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
}
define i32 @caller_large_struct_ret() nounwind {
- ; RV32I-LABEL: name: caller_large_struct_ret
- ; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; RV32I-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, implicit-def $x1, implicit $x10
- ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1)
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)
- ; RV32I-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3)
- ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
- ; RV32I-NEXT: PseudoRET implicit $x10
+ ; ILP32-LABEL: name: caller_large_struct_ret
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; ILP32-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1)
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)
+ ; ILP32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3)
+ ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; ILP32-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32F-LABEL: name: caller_large_struct_ret
+ ; ILP32F: bb.1 (%ir-block.0):
+ ; ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; ILP32F-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1)
+ ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)
+ ; ILP32F-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3)
+ ; ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; ILP32F-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; ILP32D-LABEL: name: caller_large_struct_ret
+ ; ILP32D: bb.1 (%ir-block.0):
+ ; ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; ILP32D-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1)
+ ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)
+ ; ILP32D-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3)
+ ; ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
+ ; ILP32D-NEXT: PseudoRET implicit $x10
%1 = alloca %struct.large
call void @callee_large_struct_ret(ptr sret(%struct.large) %1)
%2 = load i32, ptr %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
index 3b4aca1e6953dac..0891703fa81b3ed 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
@@ -30,7 +30,7 @@ define i32 @caller_float_in_regs() nounwind {
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
; RV32I-NEXT: $x10 = COPY [[C]](s32)
; RV32I-NEXT: $x11 = COPY [[C1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: $x10 = COPY [[COPY]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
@@ -91,7 +91,7 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-NEXT: $x15 = COPY [[UV5]](s32)
; RV32I-NEXT: $x16 = COPY [[UV6]](s32)
; RV32I-NEXT: $x17 = COPY [[UV7]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: $x10 = COPY [[COPY1]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
@@ -111,7 +111,7 @@ define float @callee_tiny_scalar_ret() nounwind {
define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-LABEL: name: caller_tiny_scalar_ret
; RV32I: bb.1 (%ir-block.0):
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, implicit-def $x1, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: $x10 = COPY [[COPY]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
index e33e279f7f48978..5a8cf02698db63e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
@@ -29,7 +29,7 @@ define i32 @caller_double_in_fpr() nounwind {
; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32)
; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10
; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
; RV32-ILP32D-NEXT: PseudoRET implicit $x10
@@ -93,7 +93,7 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)
; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)
; RV32-ILP32D-NEXT: $f10_d = COPY [[C5]](s64)
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10
; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
; RV32-ILP32D-NEXT: PseudoRET implicit $x10
@@ -153,7 +153,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-NEXT: $f17_d = COPY [[C7]](s64)
; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10
; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
; RV32-ILP32D-NEXT: PseudoRET implicit $x10
@@ -240,7 +240,7 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind
; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)
; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)
; RV32-ILP32D-NEXT: $x17 = COPY [[UV6]](s32)
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10
; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
; RV32-ILP32D-NEXT: PseudoRET implicit $x10
@@ -330,7 +330,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64)
; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)
; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10
; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
; RV32-ILP32D-NEXT: PseudoRET implicit $x10
@@ -352,7 +352,7 @@ define double @callee_double_ret() nounwind {
define i32 @caller_double_ret() nounwind {
; RV32-ILP32D-LABEL: name: caller_double_ret
; RV32-ILP32D: bb.1 (%ir-block.0):
- ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, implicit-def $x1, implicit-def $f10_d
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d
; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV32-ILP32D-NEXT: $x10 = COPY [[TRUNC]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
index 31c759adefc5344..15f68f8d73ad861 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
+; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
+; RUN: | FileCheck -check-prefixes=RV32-ILP32FD,RV32-ILP32D %s
; This file contains tests that should have identical output for the ilp32f
; and ilp32d ABIs.
@@ -26,16 +26,27 @@ define i32 @callee_float_in_fpr(i32 %a, float %b) nounwind {
}
define i32 @caller_float_in_fpr() nounwind {
- ; RV32-ILP32FD-LABEL: name: caller_float_in_fpr
- ; RV32-ILP32FD: bb.1 (%ir-block.0):
- ; RV32-ILP32FD-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; RV32-ILP32FD-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[C]](s32)
- ; RV32-ILP32FD-NEXT: $f10_f = COPY [[C1]](s32)
- ; RV32-ILP32FD-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10
- ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[COPY]](s32)
- ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10
+ ; RV32-ILP32F-LABEL: name: caller_float_in_fpr
+ ; RV32-ILP32F: bb.1 (%ir-block.0):
+ ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[C]](s32)
+ ; RV32-ILP32F-NEXT: $f10_f = COPY [[C1]](s32)
+ ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10
+ ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32-ILP32D-LABEL: name: caller_float_in_fpr
+ ; RV32-ILP32D: bb.1 (%ir-block.0):
+ ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32)
+ ; RV32-ILP32D-NEXT: $f10_f = COPY [[C1]](s32)
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $x10
+ ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
ret i32 %1
}
@@ -71,35 +82,65 @@ define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i
}
define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
- ; RV32-ILP32FD-LABEL: name: caller_float_in_fpr_exhausted_gprs
- ; RV32-ILP32FD: bb.1 (%ir-block.0):
- ; RV32-ILP32FD-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; RV32-ILP32FD-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; RV32-ILP32FD-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; RV32-ILP32FD-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; RV32-ILP32FD-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; RV32-ILP32FD-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
- ; RV32-ILP32FD-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; RV32-ILP32FD-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
- ; RV32-ILP32FD-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
- ; RV32-ILP32FD-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
- ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
- ; RV32-ILP32FD-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV32-ILP32FD-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32)
- ; RV32-ILP32FD-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[UV]](s32)
- ; RV32-ILP32FD-NEXT: $x11 = COPY [[UV1]](s32)
- ; RV32-ILP32FD-NEXT: $x12 = COPY [[UV2]](s32)
- ; RV32-ILP32FD-NEXT: $x13 = COPY [[UV3]](s32)
- ; RV32-ILP32FD-NEXT: $x14 = COPY [[UV4]](s32)
- ; RV32-ILP32FD-NEXT: $x15 = COPY [[UV5]](s32)
- ; RV32-ILP32FD-NEXT: $x16 = COPY [[UV6]](s32)
- ; RV32-ILP32FD-NEXT: $x17 = COPY [[UV7]](s32)
- ; RV32-ILP32FD-NEXT: $f10_f = COPY [[C5]](s32)
- ; RV32-ILP32FD-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10
- ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[COPY1]](s32)
- ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10
+ ; RV32-ILP32F-LABEL: name: caller_float_in_fpr_exhausted_gprs
+ ; RV32-ILP32F: bb.1 (%ir-block.0):
+ ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; RV32-ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; RV32-ILP32F-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
+ ; RV32-ILP32F-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
+ ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32)
+ ; RV32-ILP32F-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-ILP32F-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-ILP32F-NEXT: $x12 = COPY [[UV2]](s32)
+ ; RV32-ILP32F-NEXT: $x13 = COPY [[UV3]](s32)
+ ; RV32-ILP32F-NEXT: $x14 = COPY [[UV4]](s32)
+ ; RV32-ILP32F-NEXT: $x15 = COPY [[UV5]](s32)
+ ; RV32-ILP32F-NEXT: $x16 = COPY [[UV6]](s32)
+ ; RV32-ILP32F-NEXT: $x17 = COPY [[UV7]](s32)
+ ; RV32-ILP32F-NEXT: $f10_f = COPY [[C5]](s32)
+ ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10
+ ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32-ILP32D-LABEL: name: caller_float_in_fpr_exhausted_gprs
+ ; RV32-ILP32D: bb.1 (%ir-block.0):
+ ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
+ ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
+ ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32)
+ ; RV32-ILP32D-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)
+ ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)
+ ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)
+ ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)
+ ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)
+ ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)
+ ; RV32-ILP32D-NEXT: $f10_f = COPY [[C5]](s32)
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $x10
+ ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_float_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
ret i32 %1
@@ -132,30 +173,55 @@ define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, flo
}
define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
- ; RV32-ILP32FD-LABEL: name: caller_float_in_gpr_exhausted_fprs
- ; RV32-ILP32FD: bb.1 (%ir-block.0):
- ; RV32-ILP32FD-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; RV32-ILP32FD-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
- ; RV32-ILP32FD-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+00
- ; RV32-ILP32FD-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
- ; RV32-ILP32FD-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00
- ; RV32-ILP32FD-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
- ; RV32-ILP32FD-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+00
- ; RV32-ILP32FD-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
- ; RV32-ILP32FD-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
- ; RV32-ILP32FD-NEXT: $f10_f = COPY [[C]](s32)
- ; RV32-ILP32FD-NEXT: $f11_f = COPY [[C1]](s32)
- ; RV32-ILP32FD-NEXT: $f12_f = COPY [[C2]](s32)
- ; RV32-ILP32FD-NEXT: $f13_f = COPY [[C3]](s32)
- ; RV32-ILP32FD-NEXT: $f14_f = COPY [[C4]](s32)
- ; RV32-ILP32FD-NEXT: $f15_f = COPY [[C5]](s32)
- ; RV32-ILP32FD-NEXT: $f16_f = COPY [[C6]](s32)
- ; RV32-ILP32FD-NEXT: $f17_f = COPY [[C7]](s32)
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[C8]](s32)
- ; RV32-ILP32FD-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10
- ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[COPY]](s32)
- ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10
+ ; RV32-ILP32F-LABEL: name: caller_float_in_gpr_exhausted_fprs
+ ; RV32-ILP32F: bb.1 (%ir-block.0):
+ ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+00
+ ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+ ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00
+ ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+00
+ ; RV32-ILP32F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
+ ; RV32-ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
+ ; RV32-ILP32F-NEXT: $f10_f = COPY [[C]](s32)
+ ; RV32-ILP32F-NEXT: $f11_f = COPY [[C1]](s32)
+ ; RV32-ILP32F-NEXT: $f12_f = COPY [[C2]](s32)
+ ; RV32-ILP32F-NEXT: $f13_f = COPY [[C3]](s32)
+ ; RV32-ILP32F-NEXT: $f14_f = COPY [[C4]](s32)
+ ; RV32-ILP32F-NEXT: $f15_f = COPY [[C5]](s32)
+ ; RV32-ILP32F-NEXT: $f16_f = COPY [[C6]](s32)
+ ; RV32-ILP32F-NEXT: $f17_f = COPY [[C7]](s32)
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[C8]](s32)
+ ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10
+ ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32-ILP32D-LABEL: name: caller_float_in_gpr_exhausted_fprs
+ ; RV32-ILP32D: bb.1 (%ir-block.0):
+ ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+00
+ ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+ ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00
+ ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+00
+ ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
+ ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
+ ; RV32-ILP32D-NEXT: $f10_f = COPY [[C]](s32)
+ ; RV32-ILP32D-NEXT: $f11_f = COPY [[C1]](s32)
+ ; RV32-ILP32D-NEXT: $f12_f = COPY [[C2]](s32)
+ ; RV32-ILP32D-NEXT: $f13_f = COPY [[C3]](s32)
+ ; RV32-ILP32D-NEXT: $f14_f = COPY [[C4]](s32)
+ ; RV32-ILP32D-NEXT: $f15_f = COPY [[C5]](s32)
+ ; RV32-ILP32D-NEXT: $f16_f = COPY [[C6]](s32)
+ ; RV32-ILP32D-NEXT: $f17_f = COPY [[C7]](s32)
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[C8]](s32)
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $x10
+ ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_float_in_gpr_exhausted_fprs(
float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,
float 7.0, float 8.0, float 9.0)
@@ -202,49 +268,93 @@ define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c,
}
define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
- ; RV32-ILP32FD-LABEL: name: caller_float_on_stack_exhausted_gprs_fprs
- ; RV32-ILP32FD: bb.1 (%ir-block.0):
- ; RV32-ILP32FD-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; RV32-ILP32FD-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
- ; RV32-ILP32FD-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; RV32-ILP32FD-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
- ; RV32-ILP32FD-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; RV32-ILP32FD-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
- ; RV32-ILP32FD-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; RV32-ILP32FD-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
- ; RV32-ILP32FD-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
- ; RV32-ILP32FD-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01
- ; RV32-ILP32FD-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01
- ; RV32-ILP32FD-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01
- ; RV32-ILP32FD-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01
- ; RV32-ILP32FD-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
- ; RV32-ILP32FD-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
- ; RV32-ILP32FD-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
- ; RV32-ILP32FD-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
- ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
- ; RV32-ILP32FD-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV32-ILP32FD-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)
- ; RV32-ILP32FD-NEXT: G_STORE [[C12]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[UV]](s32)
- ; RV32-ILP32FD-NEXT: $x11 = COPY [[UV1]](s32)
- ; RV32-ILP32FD-NEXT: $f10_f = COPY [[C1]](s32)
- ; RV32-ILP32FD-NEXT: $x12 = COPY [[UV2]](s32)
- ; RV32-ILP32FD-NEXT: $x13 = COPY [[UV3]](s32)
- ; RV32-ILP32FD-NEXT: $f11_f = COPY [[C3]](s32)
- ; RV32-ILP32FD-NEXT: $x14 = COPY [[UV4]](s32)
- ; RV32-ILP32FD-NEXT: $x15 = COPY [[UV5]](s32)
- ; RV32-ILP32FD-NEXT: $f12_f = COPY [[C5]](s32)
- ; RV32-ILP32FD-NEXT: $x16 = COPY [[UV6]](s32)
- ; RV32-ILP32FD-NEXT: $x17 = COPY [[UV7]](s32)
- ; RV32-ILP32FD-NEXT: $f13_f = COPY [[C7]](s32)
- ; RV32-ILP32FD-NEXT: $f14_f = COPY [[C8]](s32)
- ; RV32-ILP32FD-NEXT: $f15_f = COPY [[C9]](s32)
- ; RV32-ILP32FD-NEXT: $f16_f = COPY [[C10]](s32)
- ; RV32-ILP32FD-NEXT: $f17_f = COPY [[C11]](s32)
- ; RV32-ILP32FD-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10
- ; RV32-ILP32FD-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[COPY1]](s32)
- ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10
+ ; RV32-ILP32F-LABEL: name: caller_float_on_stack_exhausted_gprs_fprs
+ ; RV32-ILP32F: bb.1 (%ir-block.0):
+ ; RV32-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RV32-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; RV32-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+ ; RV32-ILP32F-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; RV32-ILP32F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32F-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; RV32-ILP32F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
+ ; RV32-ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
+ ; RV32-ILP32F-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01
+ ; RV32-ILP32F-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01
+ ; RV32-ILP32F-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01
+ ; RV32-ILP32F-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01
+ ; RV32-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; RV32-ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
+ ; RV32-ILP32F-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
+ ; RV32-ILP32F-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
+ ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32-ILP32F-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)
+ ; RV32-ILP32F-NEXT: G_STORE [[C12]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-ILP32F-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-ILP32F-NEXT: $f10_f = COPY [[C1]](s32)
+ ; RV32-ILP32F-NEXT: $x12 = COPY [[UV2]](s32)
+ ; RV32-ILP32F-NEXT: $x13 = COPY [[UV3]](s32)
+ ; RV32-ILP32F-NEXT: $f11_f = COPY [[C3]](s32)
+ ; RV32-ILP32F-NEXT: $x14 = COPY [[UV4]](s32)
+ ; RV32-ILP32F-NEXT: $x15 = COPY [[UV5]](s32)
+ ; RV32-ILP32F-NEXT: $f12_f = COPY [[C5]](s32)
+ ; RV32-ILP32F-NEXT: $x16 = COPY [[UV6]](s32)
+ ; RV32-ILP32F-NEXT: $x17 = COPY [[UV7]](s32)
+ ; RV32-ILP32F-NEXT: $f13_f = COPY [[C7]](s32)
+ ; RV32-ILP32F-NEXT: $f14_f = COPY [[C8]](s32)
+ ; RV32-ILP32F-NEXT: $f15_f = COPY [[C9]](s32)
+ ; RV32-ILP32F-NEXT: $f16_f = COPY [[C10]](s32)
+ ; RV32-ILP32F-NEXT: $f17_f = COPY [[C11]](s32)
+ ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10
+ ; RV32-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32-ILP32D-LABEL: name: caller_float_on_stack_exhausted_gprs_fprs
+ ; RV32-ILP32D: bb.1 (%ir-block.0):
+ ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+ ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
+ ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
+ ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+00
+ ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01
+ ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01
+ ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01
+ ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01
+ ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
+ ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
+ ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
+ ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
+ ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)
+ ; RV32-ILP32D-NEXT: G_STORE [[C12]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-ILP32D-NEXT: $f10_f = COPY [[C1]](s32)
+ ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)
+ ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)
+ ; RV32-ILP32D-NEXT: $f11_f = COPY [[C3]](s32)
+ ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)
+ ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)
+ ; RV32-ILP32D-NEXT: $f12_f = COPY [[C5]](s32)
+ ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)
+ ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)
+ ; RV32-ILP32D-NEXT: $f13_f = COPY [[C7]](s32)
+ ; RV32-ILP32D-NEXT: $f14_f = COPY [[C8]](s32)
+ ; RV32-ILP32D-NEXT: $f15_f = COPY [[C9]](s32)
+ ; RV32-ILP32D-NEXT: $f16_f = COPY [[C10]](s32)
+ ; RV32-ILP32D-NEXT: $f17_f = COPY [[C11]](s32)
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_f, implicit $x12, implicit $x13, implicit $f11_f, implicit $x14, implicit $x15, implicit $f12_f, implicit $x16, implicit $x17, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit-def $x10
+ ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
+ ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
@@ -261,12 +371,19 @@ define float @callee_float_ret() nounwind {
}
define i32 @caller_float_ret() nounwind {
- ; RV32-ILP32FD-LABEL: name: caller_float_ret
- ; RV32-ILP32FD: bb.1 (%ir-block.0):
- ; RV32-ILP32FD-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, implicit-def $x1, implicit-def $f10_f
- ; RV32-ILP32FD-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-ILP32FD-NEXT: $x10 = COPY [[COPY]](s32)
- ; RV32-ILP32FD-NEXT: PseudoRET implicit $x10
+ ; RV32-ILP32F-LABEL: name: caller_float_ret
+ ; RV32-ILP32F: bb.1 (%ir-block.0):
+ ; RV32-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $f10_f
+ ; RV32-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-ILP32F-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32-ILP32D-LABEL: name: caller_float_ret
+ ; RV32-ILP32D: bb.1 (%ir-block.0):
+ ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_f
+ ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
+ ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
%1 = call float @callee_float_ret()
%2 = bitcast float %1 to i32
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
index 4d6275db77bc895..af02490dff56a9d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64I,LP64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64I,LP64F %s
; This file contains tests that should have identical output for the lp64 and
; lp64f ABIs.
@@ -26,16 +26,27 @@ define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
}
define i64 @caller_double_in_regs() nounwind {
- ; RV64I-LABEL: name: caller_double_in_regs
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
- ; RV64I-NEXT: $x10 = COPY [[C]](s64)
- ; RV64I-NEXT: $x11 = COPY [[C1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_double_in_regs
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; LP64-NEXT: $x10 = COPY [[C]](s64)
+ ; LP64-NEXT: $x11 = COPY [[C1]](s64)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_double_in_regs
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; LP64F-NEXT: $x10 = COPY [[C]](s64)
+ ; LP64F-NEXT: $x11 = COPY [[C1]](s64)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
%1 = call i64 @callee_double_in_regs(i64 1, double 2.0)
ret i64 %1
}
@@ -50,12 +61,19 @@ define double @callee_double_ret() nounwind {
}
define i64 @caller_double_ret() nounwind {
- ; RV64I-LABEL: name: caller_double_ret
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, implicit-def $x1, implicit-def $x10
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_double_ret
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_double_ret
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
%1 = call double @callee_double_ret()
%2 = bitcast double %1 to i64
ret i64 %2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
index 8533ed77b557029..9e78dcf219bd123 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64I,LP64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64I,LP64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \
; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: | FileCheck -check-prefixes=RV64I,LP64D %s
; This file contains tests that should have identical output for the lp64,
; lp64f, and lp64d ABIs. i.e. where no arguments are passed according to
@@ -35,18 +35,44 @@ define i64 @callee_i128_in_regs(i64 %a, i128 %b) nounwind {
}
define i64 @caller_i128_in_regs() nounwind {
- ; RV64I-LABEL: name: caller_i128_in_regs
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2
- ; RV64I-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
- ; RV64I-NEXT: $x10 = COPY [[C]](s64)
- ; RV64I-NEXT: $x11 = COPY [[UV]](s64)
- ; RV64I-NEXT: $x12 = COPY [[UV1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_i128_in_regs
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2
+ ; LP64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
+ ; LP64-NEXT: $x10 = COPY [[C]](s64)
+ ; LP64-NEXT: $x11 = COPY [[UV]](s64)
+ ; LP64-NEXT: $x12 = COPY [[UV1]](s64)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_i128_in_regs
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2
+ ; LP64F-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
+ ; LP64F-NEXT: $x10 = COPY [[C]](s64)
+ ; LP64F-NEXT: $x11 = COPY [[UV]](s64)
+ ; LP64F-NEXT: $x12 = COPY [[UV1]](s64)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: caller_i128_in_regs
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2
+ ; LP64D-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
+ ; LP64D-NEXT: $x10 = COPY [[C]](s64)
+ ; LP64D-NEXT: $x11 = COPY [[UV]](s64)
+ ; LP64D-NEXT: $x12 = COPY [[UV1]](s64)
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_i128_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64D-NEXT: $x10 = COPY [[COPY]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
%1 = call i64 @callee_i128_in_regs(i64 1, i128 2)
ret i64 %1
}
@@ -105,45 +131,125 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
}
define i32 @caller_many_scalars() nounwind {
- ; RV64I-LABEL: name: caller_many_scalars
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s128) = G_CONSTANT i128 4
- ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s128) = G_CONSTANT i128 7
- ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s8)
- ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
- ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
- ; RV64I-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C3]](s128)
- ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
- ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
- ; RV64I-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C6]](s128)
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
- ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; RV64I-NEXT: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
- ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
- ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; RV64I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; RV64I-NEXT: G_STORE [[ANYEXT5]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
- ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
- ; RV64I-NEXT: $x12 = COPY [[ANYEXT2]](s64)
- ; RV64I-NEXT: $x13 = COPY [[UV]](s64)
- ; RV64I-NEXT: $x14 = COPY [[UV1]](s64)
- ; RV64I-NEXT: $x15 = COPY [[ANYEXT3]](s64)
- ; RV64I-NEXT: $x16 = COPY [[ANYEXT4]](s64)
- ; RV64I-NEXT: $x17 = COPY [[UV2]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
- ; RV64I-NEXT: $x10 = COPY [[ANYEXT6]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_many_scalars
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; LP64-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; LP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; LP64-NEXT: [[C3:%[0-9]+]]:_(s128) = G_CONSTANT i128 4
+ ; LP64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; LP64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; LP64-NEXT: [[C6:%[0-9]+]]:_(s128) = G_CONSTANT i128 7
+ ; LP64-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s8)
+ ; LP64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
+ ; LP64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
+ ; LP64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C3]](s128)
+ ; LP64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
+ ; LP64-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
+ ; LP64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C6]](s128)
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; LP64-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
+ ; LP64-NEXT: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
+ ; LP64-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; LP64-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; LP64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
+ ; LP64-NEXT: G_STORE [[ANYEXT5]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8)
+ ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64-NEXT: $x11 = COPY [[ANYEXT1]](s64)
+ ; LP64-NEXT: $x12 = COPY [[ANYEXT2]](s64)
+ ; LP64-NEXT: $x13 = COPY [[UV]](s64)
+ ; LP64-NEXT: $x14 = COPY [[UV1]](s64)
+ ; LP64-NEXT: $x15 = COPY [[ANYEXT3]](s64)
+ ; LP64-NEXT: $x16 = COPY [[ANYEXT4]](s64)
+ ; LP64-NEXT: $x17 = COPY [[UV2]](s64)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; LP64-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
+ ; LP64-NEXT: $x10 = COPY [[ANYEXT6]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_many_scalars
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; LP64F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; LP64F-NEXT: [[C3:%[0-9]+]]:_(s128) = G_CONSTANT i128 4
+ ; LP64F-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; LP64F-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; LP64F-NEXT: [[C6:%[0-9]+]]:_(s128) = G_CONSTANT i128 7
+ ; LP64F-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s8)
+ ; LP64F-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
+ ; LP64F-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
+ ; LP64F-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C3]](s128)
+ ; LP64F-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
+ ; LP64F-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
+ ; LP64F-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C6]](s128)
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; LP64F-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
+ ; LP64F-NEXT: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
+ ; LP64F-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; LP64F-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; LP64F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
+ ; LP64F-NEXT: G_STORE [[ANYEXT5]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8)
+ ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64F-NEXT: $x11 = COPY [[ANYEXT1]](s64)
+ ; LP64F-NEXT: $x12 = COPY [[ANYEXT2]](s64)
+ ; LP64F-NEXT: $x13 = COPY [[UV]](s64)
+ ; LP64F-NEXT: $x14 = COPY [[UV1]](s64)
+ ; LP64F-NEXT: $x15 = COPY [[ANYEXT3]](s64)
+ ; LP64F-NEXT: $x16 = COPY [[ANYEXT4]](s64)
+ ; LP64F-NEXT: $x17 = COPY [[UV2]](s64)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; LP64F-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
+ ; LP64F-NEXT: $x10 = COPY [[ANYEXT6]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: caller_many_scalars
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; LP64D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; LP64D-NEXT: [[C3:%[0-9]+]]:_(s128) = G_CONSTANT i128 4
+ ; LP64D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; LP64D-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+ ; LP64D-NEXT: [[C6:%[0-9]+]]:_(s128) = G_CONSTANT i128 7
+ ; LP64D-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s8)
+ ; LP64D-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
+ ; LP64D-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
+ ; LP64D-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C3]](s128)
+ ; LP64D-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
+ ; LP64D-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
+ ; LP64D-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C6]](s128)
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
+ ; LP64D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
+ ; LP64D-NEXT: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
+ ; LP64D-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
+ ; LP64D-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; LP64D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
+ ; LP64D-NEXT: G_STORE [[ANYEXT5]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8)
+ ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64D-NEXT: $x11 = COPY [[ANYEXT1]](s64)
+ ; LP64D-NEXT: $x12 = COPY [[ANYEXT2]](s64)
+ ; LP64D-NEXT: $x13 = COPY [[UV]](s64)
+ ; LP64D-NEXT: $x14 = COPY [[UV1]](s64)
+ ; LP64D-NEXT: $x15 = COPY [[ANYEXT3]](s64)
+ ; LP64D-NEXT: $x16 = COPY [[ANYEXT4]](s64)
+ ; LP64D-NEXT: $x17 = COPY [[UV2]](s64)
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_many_scalars, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
+ ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; LP64D-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
+ ; LP64D-NEXT: $x10 = COPY [[ANYEXT6]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8)
ret i32 %1
}
@@ -162,17 +268,41 @@ define i128 @callee_small_scalar_ret() nounwind {
}
define i64 @caller_small_scalar_ret() nounwind {
- ; RV64I-LABEL: name: caller_small_scalar_ret
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, implicit-def $x1, implicit-def $x10, implicit-def $x11
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; RV64I-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s128), [[MV]]
- ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ICMP]](s1)
- ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_small_scalar_ret
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+ ; LP64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s128), [[MV]]
+ ; LP64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ICMP]](s1)
+ ; LP64-NEXT: $x10 = COPY [[ZEXT]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_small_scalar_ret
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64F-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+ ; LP64F-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s128), [[MV]]
+ ; LP64F-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ICMP]](s1)
+ ; LP64F-NEXT: $x10 = COPY [[ZEXT]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: caller_small_scalar_ret
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -2
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_scalar_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64D-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+ ; LP64D-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[C]](s128), [[MV]]
+ ; LP64D-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ICMP]](s1)
+ ; LP64D-NEXT: $x10 = COPY [[ZEXT]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
%1 = call i128 @callee_small_scalar_ret()
%2 = icmp eq i128 -2, %1
%3 = zext i1 %2 to i64
@@ -195,15 +325,35 @@ define %struct.small @callee_small_struct_ret() nounwind {
}
define i64 @caller_small_struct_ret() nounwind {
- ; RV64I-LABEL: name: caller_small_struct_ret
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, implicit-def $x1, implicit-def $x10, implicit-def $x11
- ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RV64I-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[PTRTOINT]]
- ; RV64I-NEXT: $x10 = COPY [[ADD]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_small_struct_ret
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; LP64-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; LP64-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_small_struct_ret
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; LP64F-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; LP64F-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: caller_small_struct_ret
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_small_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; LP64D-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+ ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[PTRTOINT]]
+ ; LP64D-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
%1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1
@@ -248,18 +398,44 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
}
define i64 @caller_large_struct_ret() nounwind {
- ; RV64I-LABEL: name: caller_large_struct_ret
- ; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; RV64I-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, implicit-def $x1, implicit $x10
- ; RV64I-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1)
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; RV64I-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3)
- ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]
- ; RV64I-NEXT: $x10 = COPY [[ADD]](s64)
- ; RV64I-NEXT: PseudoRET implicit $x10
+ ; LP64-LABEL: name: caller_large_struct_ret
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; LP64-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1)
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; LP64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3)
+ ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]
+ ; LP64-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: caller_large_struct_ret
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; LP64F-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1)
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; LP64F-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3)
+ ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]
+ ; LP64F-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: caller_large_struct_ret
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; LP64D-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @callee_large_struct_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1)
+ ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; LP64D-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3)
+ ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]
+ ; LP64D-NEXT: $x10 = COPY [[ADD]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
%1 = alloca %struct.large
call void @callee_large_struct_ret(ptr sret(%struct.large) %1)
%2 = load i64, ptr %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
index a45af04c09b21c6..ab0e296d0c7a415 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
@@ -36,7 +36,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
; RV64I-NEXT: $x10 = COPY [[C]](s64)
; RV64I-NEXT: $x11 = COPY [[ANYEXT]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
@@ -48,7 +48,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64F-NEXT: $x10 = COPY [[C]](s64)
; RV64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
; RV64F-NEXT: $x11 = COPY [[ANYEXT]](s64)
- ; RV64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; RV64F-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; RV64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64F-NEXT: $x10 = COPY [[COPY]](s64)
; RV64F-NEXT: PseudoRET implicit $x10
@@ -69,7 +69,7 @@ define float @callee_tiny_scalar_ret() nounwind {
define i64 @caller_tiny_scalar_ret() nounwind {
; RV64-LABEL: name: caller_tiny_scalar_ret
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, implicit-def $x1, implicit-def $x10
+ ; RV64-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
index 90ab171dd55a95d..e5323751c7ab2af 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
@@ -29,7 +29,7 @@ define i64 @caller_double_in_regs() nounwind {
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; RV64I-NEXT: $x10 = COPY [[C]](s64)
; RV64I-NEXT: $f10_d = COPY [[C1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_regs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
@@ -93,7 +93,7 @@ define i64 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV64I-NEXT: $x16 = COPY [[UV6]](s64)
; RV64I-NEXT: $x17 = COPY [[UV7]](s64)
; RV64I-NEXT: $f10_d = COPY [[C5]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: $x10 = COPY [[COPY1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
@@ -150,7 +150,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV64I-NEXT: $f16_d = COPY [[C6]](s64)
; RV64I-NEXT: $f17_d = COPY [[C7]](s64)
; RV64I-NEXT: $x10 = COPY [[C8]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
@@ -241,7 +241,7 @@ define i64 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV64I-NEXT: $f15_d = COPY [[C9]](s64)
; RV64I-NEXT: $f16_d = COPY [[C10]](s64)
; RV64I-NEXT: $f17_d = COPY [[C11]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: $x10 = COPY [[COPY1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
@@ -263,7 +263,7 @@ define double @callee_double_ret() nounwind {
define i64 @caller_double_ret() nounwind {
; RV64I-LABEL: name: caller_double_ret
; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, implicit-def $x1, implicit-def $f10_d
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
; RV64I-NEXT: $x10 = COPY [[COPY]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
index 8375acf5e1ee4c0..022f62c1afdba20 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
@@ -10,11 +10,12 @@ define void @test_call_void_noargs() {
; RV32I-LABEL: name: test_call_void_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, implicit-def $x1
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, csr_ilp32_lp64, implicit-def $x1
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, implicit-def $x1
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_noargs, csr_ilp32_lp64, implicit-def $x1
; RV64I-NEXT: PseudoRET
entry:
call void @void_noargs()
@@ -33,8 +34,9 @@ define void @test_call_void_args_i8() {
; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s8)
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_args_i8
; RV64I: bb.1.entry:
; RV64I-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
@@ -43,7 +45,7 @@ define void @test_call_void_args_i8() {
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s8)
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV64I-NEXT: PseudoRET
entry:
call void @void_args_i8(i8 0, i8 1)
@@ -62,8 +64,9 @@ define void @test_call_void_args_i8_zext() {
; RV32I-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[C1]](s8)
; RV32I-NEXT: $x10 = COPY [[ZEXT]](s32)
; RV32I-NEXT: $x11 = COPY [[ZEXT1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_args_i8_zext
; RV64I: bb.1.entry:
; RV64I-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
@@ -72,7 +75,7 @@ define void @test_call_void_args_i8_zext() {
; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s8)
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
; RV64I-NEXT: $x11 = COPY [[ZEXT1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i8_zext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV64I-NEXT: PseudoRET
entry:
call void @void_args_i8_zext(i8 zeroext 0, i8 zeroext 1)
@@ -91,8 +94,9 @@ define void @test_call_void_args_i16_sext() {
; RV32I-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
; RV32I-NEXT: $x10 = COPY [[SEXT]](s32)
; RV32I-NEXT: $x11 = COPY [[SEXT1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_args_i16_sext
; RV64I: bb.1.entry:
; RV64I-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
@@ -101,7 +105,7 @@ define void @test_call_void_args_i16_sext() {
; RV64I-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[C1]](s16)
; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
; RV64I-NEXT: $x11 = COPY [[SEXT1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i16_sext, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV64I-NEXT: PseudoRET
entry:
call void @void_args_i16_sext(i16 signext 0, i16 signext 1)
@@ -118,8 +122,9 @@ define void @test_call_void_args_i32() {
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; RV32I-NEXT: $x10 = COPY [[C]](s32)
; RV32I-NEXT: $x11 = COPY [[C1]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_args_i32
; RV64I: bb.1.entry:
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -128,7 +133,7 @@ define void @test_call_void_args_i32() {
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i32, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV64I-NEXT: PseudoRET
entry:
call void @void_args_i32(i32 0, i32 1)
@@ -149,15 +154,16 @@ define void @test_call_void_args_i64() {
; RV32I-NEXT: $x11 = COPY [[UV1]](s32)
; RV32I-NEXT: $x12 = COPY [[UV2]](s32)
; RV32I-NEXT: $x13 = COPY [[UV3]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_void_args_i64
; RV64I: bb.1.entry:
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; RV64I-NEXT: $x10 = COPY [[C]](s64)
; RV64I-NEXT: $x11 = COPY [[C1]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, implicit-def $x1, implicit $x10, implicit $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_args_i64, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11
; RV64I-NEXT: PseudoRET
entry:
call void @void_args_i64(i64 0, i64 1)
@@ -170,13 +176,14 @@ define void @test_call_i8_noargs() {
; RV32I-LABEL: name: test_call_i8_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, implicit-def $x1, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_i8_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, implicit-def $x1, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i8_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: PseudoRET
@@ -191,13 +198,14 @@ define void @test_call_i16_noargs() {
; RV32I-LABEL: name: test_call_i16_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, implicit-def $x1, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_i16_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, implicit-def $x1, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i16_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: PseudoRET
@@ -212,12 +220,13 @@ define void @test_call_i32_noargs() {
; RV32I-LABEL: name: test_call_i32_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, implicit-def $x1, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_i32_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, implicit-def $x1, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: PseudoRET
@@ -232,14 +241,15 @@ define void @test_call_i64_noargs() {
; RV32I-LABEL: name: test_call_i64_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32I-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_i64_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, implicit-def $x1, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i64_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: PseudoRET
entry:
@@ -252,12 +262,13 @@ declare ptr @ptr_noargs()
define void @test_call_ptr_noargs() {
; RV32I-LABEL: name: test_call_ptr_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, implicit-def $x1, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_ptr_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, implicit-def $x1, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @ptr_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; RV64I-NEXT: PseudoRET
entry:
@@ -270,13 +281,14 @@ declare [2 x i32] @i32x2_noargs()
define void @test_call_i32x2_noargs() {
; RV32I-LABEL: name: test_call_i32x2_noargs
; RV32I: bb.1.entry:
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_call_i32x2_noargs
; RV64I: bb.1.entry:
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, implicit-def $x1, implicit-def $x10, implicit-def $x11
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @i32x2_noargs, csr_ilp32_lp64, implicit-def $x1, implicit-def $x10, implicit-def $x11
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
@@ -297,13 +309,14 @@ define void @test_void_byval_args() {
; RV32I: bb.1.entry:
; RV32I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo
; RV32I-NEXT: $x10 = COPY [[GV]](p0)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, implicit-def $x1, implicit $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_void_byval_args
; RV64I: bb.1.entry:
; RV64I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo
; RV64I-NEXT: $x10 = COPY [[GV]](p0)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, implicit-def $x1, implicit $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_byval_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; RV64I-NEXT: PseudoRET
entry:
call void @void_byval_args(ptr byval(%struct.Foo) @foo)
@@ -317,13 +330,14 @@ define void @test_void_sret_args() {
; RV32I: bb.1.entry:
; RV32I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo
; RV32I-NEXT: $x10 = COPY [[GV]](p0)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, implicit-def $x1, implicit $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; RV32I-NEXT: PseudoRET
+ ;
; RV64I-LABEL: name: test_void_sret_args
; RV64I: bb.1.entry:
; RV64I-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @foo
; RV64I-NEXT: $x10 = COPY [[GV]](p0)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, implicit-def $x1, implicit $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @void_sret_args, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; RV64I-NEXT: PseudoRET
entry:
call void @void_sret_args(ptr sret(%struct.Foo) @foo)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
index d0f962c301130c5..dd41664c8d60502 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
@@ -19,7 +19,7 @@ define i32 @main() {
; RV32I-NEXT: $x11 = COPY [[C1]](s32)
; RV32I-NEXT: $x12 = COPY [[C2]](s32)
; RV32I-NEXT: $x13 = COPY [[C3]](s32)
- ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @foo, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10
+ ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32I-NEXT: $x10 = COPY [[COPY]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
@@ -37,7 +37,7 @@ define i32 @main() {
; RV64I-NEXT: $x11 = COPY [[C2]](s64)
; RV64I-NEXT: $x12 = COPY [[C3]](s64)
; RV64I-NEXT: $x13 = COPY [[C4]](s64)
- ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @foo, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10
+ ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
; RV64I-NEXT: $x10 = COPY [[ASSERT_SEXT]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir
index c459a2e46afd206..19891db1210a6a4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir
@@ -18,7 +18,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -60,7 +60,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -102,7 +102,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -138,7 +138,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -175,7 +175,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x12 = COPY %ylo(s32)
; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -197,7 +197,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32)
; CHECK-M-NEXT: $x12 = COPY %ylo(s32)
; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -232,7 +232,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s32)
; CHECK-I-NEXT: $x12 = COPY %lo2(s32)
; CHECK-I-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -248,7 +248,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s32)
; CHECK-M-NEXT: $x12 = COPY %lo2(s32)
; CHECK-M-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -280,7 +280,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -318,7 +318,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -356,7 +356,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -390,7 +390,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -429,7 +429,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32)
; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -453,7 +453,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32)
; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32)
; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -488,7 +488,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s32)
; CHECK-I-NEXT: $x12 = COPY %lo2(s32)
; CHECK-I-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -504,7 +504,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s32)
; CHECK-M-NEXT: $x12 = COPY %lo2(s32)
; CHECK-M-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
index 19e5c38f28c0cf2..f85cf0de30b09f7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -56,7 +56,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -79,7 +79,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -103,7 +103,7 @@ body: |
; CHECK-NEXT: $x11 = COPY %hi1(s32)
; CHECK-NEXT: $x12 = COPY %lo2(s32)
; CHECK-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
@@ -137,7 +137,7 @@ body: |
; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
; CHECK-NEXT: $x12 = COPY [[COPY1]](s32)
; CHECK-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir
index 43fd1f99fdcafe8..052fbd6580b5a13 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir
@@ -45,7 +45,7 @@ body: |
; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32)
; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
@@ -105,7 +105,7 @@ body: |
; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32)
; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
@@ -159,7 +159,7 @@ body: |
; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s32)
; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32)
; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -218,7 +218,7 @@ body: |
; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; LIBCALL-NEXT: $x10 = COPY [[AND]](s32)
; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
@@ -272,7 +272,7 @@ body: |
; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; LIBCALL-NEXT: $x10 = COPY [[AND]](s32)
; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
@@ -322,7 +322,7 @@ body: |
; LIBCALL-NEXT: $x11 = COPY [[C]](s32)
; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32)
; LIBCALL-NEXT: $x13 = COPY [[C1]](s32)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir
index 97612d6b9fde03b..d918148e6dbf78d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir
@@ -18,7 +18,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -60,7 +60,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -102,7 +102,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -138,7 +138,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -175,7 +175,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32)
; CHECK-I-NEXT: $x12 = COPY %ylo(s32)
; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -197,7 +197,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32)
; CHECK-M-NEXT: $x12 = COPY %ylo(s32)
; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -232,7 +232,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s32)
; CHECK-I-NEXT: $x12 = COPY %lo2(s32)
; CHECK-I-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -248,7 +248,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s32)
; CHECK-M-NEXT: $x12 = COPY %lo2(s32)
; CHECK-M-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -280,7 +280,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -318,7 +318,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -356,7 +356,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -390,7 +390,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -429,7 +429,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32)
; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32)
; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -453,7 +453,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32)
; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32)
; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
@@ -488,7 +488,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s32)
; CHECK-I-NEXT: $x12 = COPY %lo2(s32)
; CHECK-I-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32)
@@ -504,7 +504,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s32)
; CHECK-M-NEXT: $x12 = COPY %lo2(s32)
; CHECK-M-NEXT: $x13 = COPY %hi2(s32)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
index 63361e903577c5b..9db1d44e9f0977f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
@@ -18,7 +18,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -63,7 +63,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -108,7 +108,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -149,7 +149,7 @@ body: |
; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -182,7 +182,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -219,7 +219,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x12 = COPY %ylo(s64)
; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -241,7 +241,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-M-NEXT: $x12 = COPY %ylo(s64)
; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -276,7 +276,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -292,7 +292,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -324,7 +324,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -365,7 +365,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -406,7 +406,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -447,7 +447,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -480,7 +480,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -519,7 +519,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -543,7 +543,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -578,7 +578,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -594,7 +594,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir
index d1ff3a9f574573a..4cdec96a561cfd6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -56,7 +56,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -79,7 +79,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -102,7 +102,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -126,7 +126,7 @@ body: |
; CHECK-NEXT: $x11 = COPY %hi1(s64)
; CHECK-NEXT: $x12 = COPY %lo2(s64)
; CHECK-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
@@ -160,7 +160,7 @@ body: |
; CHECK-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-NEXT: $x12 = COPY [[COPY1]](s64)
; CHECK-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir
index 7e1ec1e0961d74a..8a0917c5044dac8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir
@@ -45,7 +45,7 @@ body: |
; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64)
; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C2]](s64)
@@ -105,7 +105,7 @@ body: |
; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64)
; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C2]](s64)
@@ -155,7 +155,7 @@ body: |
; LIBCALL-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; LIBCALL-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; LIBCALL-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 32
; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[SEXT_INREG2]]
@@ -207,7 +207,7 @@ body: |
; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s64)
; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64)
; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
@@ -266,7 +266,7 @@ body: |
; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; LIBCALL-NEXT: $x10 = COPY [[AND]](s64)
; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
@@ -320,7 +320,7 @@ body: |
; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; LIBCALL-NEXT: $x10 = COPY [[AND]](s64)
; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
@@ -374,7 +374,7 @@ body: |
; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; LIBCALL-NEXT: $x10 = COPY [[AND]](s64)
; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]]
@@ -424,7 +424,7 @@ body: |
; LIBCALL-NEXT: $x11 = COPY [[C]](s64)
; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64)
; LIBCALL-NEXT: $x13 = COPY [[C1]](s64)
- ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11
; LIBCALL-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir
index f076b5988948d1f..dca7936692118c5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir
@@ -18,7 +18,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -63,7 +63,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -108,7 +108,7 @@ body: |
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -149,7 +149,7 @@ body: |
; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -182,7 +182,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -219,7 +219,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x12 = COPY %ylo(s64)
; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -241,7 +241,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-M-NEXT: $x12 = COPY %ylo(s64)
; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -276,7 +276,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -292,7 +292,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -324,7 +324,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -365,7 +365,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -406,7 +406,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -447,7 +447,7 @@ body: |
; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -480,7 +480,7 @@ body: |
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10
@@ -519,7 +519,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -543,7 +543,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
@@ -578,7 +578,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
@@ -594,7 +594,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
- ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+ ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64)
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