[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -83,6 +84,10 @@ static cl::opt<bool>
                    cl::desc("Enable sinking and folding of instruction copies"),
                    cl::init(false), cl::Hidden);
 
+static cl::opt<bool> EnableSplitRA("riscv-split-RA", cl::Hidden,
+                                   cl::desc("Enable Split RA for RVV"),
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BeMg wrote:

Fixed

https://github.com/llvm/llvm-project/pull/70549