[llvm] 4fe0d35 - [RISCV][GISel] Refactor most of selectConstant into a general constant materialization function.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-04T11:39:35-07:00
New Revision: 4fe0d35f7c4cc03fc8a27533384e7fd834721173

URL: https://github.com/llvm/llvm-project/commit/4fe0d35f7c4cc03fc8a27533384e7fd834721173
DIFF: https://github.com/llvm/llvm-project/commit/4fe0d35f7c4cc03fc8a27533384e7fd834721173.diff

LOG: [RISCV][GISel] Refactor most of selectConstant into a general constant materialization function.

Move the G_CONSTANT specific parts up to the switch that calls it.

The materialization function will be used by G_FCONSTANT too.

The only functional change is we now create COPY from X0 for the 0
case instead of changing the G_CONSTANT in place.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 698168f6a8012e9..69364fe00eaf810 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -61,8 +61,7 @@ class RISCVInstructionSelector : public InstructionSelector {
 
   // Custom selection methods
   bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
-  bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
-                      MachineRegisterInfo &MRI) const;
+  bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
   bool selectGlobalValue(MachineInstr &MI, MachineIRBuilder &MIB,
                          MachineRegisterInfo &MRI) const;
   bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
@@ -348,8 +347,16 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_TRUNC:
     return selectCopy(MI, MRI);
-  case TargetOpcode::G_CONSTANT:
-    return selectConstant(MI, MIB, MRI);
+  case TargetOpcode::G_CONSTANT: {
+    Register DstReg = MI.getOperand(0).getReg();
+    int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue();
+
+    if (!materializeImm(DstReg, Imm, MIB))
+      return false;
+
+    MI.eraseFromParent();
+    return true;
+  }
   case TargetOpcode::G_GLOBAL_VALUE:
     return selectGlobalValue(MI, MIB, MRI);
   case TargetOpcode::G_BRCOND: {
@@ -485,17 +492,13 @@ bool RISCVInstructionSelector::selectCopy(MachineInstr &MI,
   return true;
 }
 
-bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
-                                              MachineIRBuilder &MIB,
-                                              MachineRegisterInfo &MRI) const {
-  assert(MI.getOpcode() == TargetOpcode::G_CONSTANT);
-  Register FinalReg = MI.getOperand(0).getReg();
-  int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue();
+bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm,
+                                              MachineIRBuilder &MIB) const {
+  MachineRegisterInfo &MRI = *MIB.getMRI();
 
   if (Imm == 0) {
-    MI.getOperand(1).ChangeToRegister(RISCV::X0, false);
-    RBI.constrainGenericRegister(FinalReg, RISCV::GPRRegClass, MRI);
-    MI.setDesc(TII.get(TargetOpcode::COPY));
+    MIB.buildCopy(DstReg, Register(RISCV::X0));
+    RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, MRI);
     return true;
   }
 
@@ -505,9 +508,9 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
   Register SrcReg = RISCV::X0;
 
   for (unsigned i = 0; i < NumInsts; i++) {
-    Register DstReg = i < NumInsts - 1
+    Register TmpReg = i < NumInsts - 1
                           ? MRI.createVirtualRegister(&RISCV::GPRRegClass)
-                          : FinalReg;
+                          : DstReg;
     const RISCVMatInt::Inst &I = Seq[i];
     MachineInstr *Result;
 
@@ -515,25 +518,25 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
     case RISCVMatInt::Imm:
       // clang-format off
       Result = MIB.buildInstr(I.getOpcode())
-                   .addDef(DstReg)
+                   .addDef(TmpReg)
                    .addImm(I.getImm());
       // clang-format on
       break;
     case RISCVMatInt::RegX0:
       Result = MIB.buildInstr(I.getOpcode())
-                   .addDef(DstReg)
+                   .addDef(TmpReg)
                    .addReg(SrcReg)
                    .addReg(RISCV::X0);
       break;
     case RISCVMatInt::RegReg:
       Result = MIB.buildInstr(I.getOpcode())
-                   .addDef(DstReg)
+                   .addDef(TmpReg)
                    .addReg(SrcReg)
                    .addReg(SrcReg);
       break;
     case RISCVMatInt::RegImm:
       Result = MIB.buildInstr(I.getOpcode())
-                   .addDef(DstReg)
+                   .addDef(TmpReg)
                    .addReg(SrcReg)
                    .addImm(I.getImm());
       break;
@@ -542,10 +545,9 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
     if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
       return false;
 
-    SrcReg = DstReg;
+    SrcReg = TmpReg;
   }
 
-  MI.eraseFromParent();
   return true;
 }