[llvm] [AArch64][GlobalISel] Improve and expand fcopysign lowering (PR #71283)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff 3d870434b8310499ffb56f5294511344cf093cb4 a39ed08383c86f5e45b4035058936feae5c652d1 -- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 7365d5882..9eabc9e95 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -274,8 +274,9 @@ MachineIRBuilder::buildDeleteTrailingVectorElements(const DstOp &Res,
           (ResTy.isVector() &&
            (ResTy.getElementType() == Op0Ty.getElementType()))) &&
          "Different vector element types");
-  assert((ResTy.isScalar() || (ResTy.getNumElements() < Op0Ty.getNumElements())) &&
-         "Op0 has fewer elements");
+  assert(
+      (ResTy.isScalar() || (ResTy.getNumElements() < Op0Ty.getNumElements())) &&
+      "Op0 has fewer elements");
 
   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
   if (ResTy.isScalar())

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https://github.com/llvm/llvm-project/pull/71283