[llvm] [AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (PR #68186)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 3 10:47:30 PDT 2023
================
@@ -665,6 +665,50 @@ def : GCNPat<
(SI_TCRETURN_GFX Gfx_CCR_SGPR_64:$src0, (i64 0), i32imm:$fpdiff)
>;
+// Pseudo for the llvm.amdgcn.cs.chain intrinsic.
+// This is essentially a tail call, but it also takes a mask to put in EXEC
+// right before jumping to the callee.
+class SI_CS_CHAIN_TC<
+ ValueType execvt,
+ RegisterOperand execrc = !if(!eq(execvt, i32), SSrc_b32, SSrc_b64)>
+ : SPseudoInstSI <(outs),
+ (ins CCR_SGPR_64:$src0, unknown:$callee, i32imm:$fpdiff, execrc:$exec)> {
+ let FixedSize = 0;
+ let isCall = 1;
+ let isTerminator = 1;
+ let isBarrier = 1;
+ let isReturn = 1;
+ let UseNamedOperandTable = 1;
+ let SchedRW = [WriteBranch];
+ let isConvergent = 1;
+
+ let WaveSizePredicate = !if(!eq(execvt, i32), isWave32, isWave64);
----------------
jayfoad wrote:
It's a matter of taste I guess, but you could just pass the predicate in as a second template argument.
https://github.com/llvm/llvm-project/pull/68186
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