[llvm] [X86InstrInfo] support memfold on spillable inline asm (PR #70832)

[Matthias Braun via llvm-commits]

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@@ -10333,5 +10333,15 @@ void X86InstrInfo::genAlternativeCodeSequence(
   }
 }
 
+// See also: X86DAGToDAGISel::SelectInlineAsmMemoryOperand().
+void X86InstrInfo::getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops) const {
+  Ops.append({
+    MachineOperand::CreateImm(1),        // Scale
+    MachineOperand::CreateReg(0, false), // Index
+    MachineOperand::CreateImm(0),        // Disp
+    MachineOperand::CreateReg(0, false), // Segment
+  });
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MatzeB wrote:

I was wondering if this could/should be expressed with `X86AddressMode`.
`X86AddressMode M; M.getFullAddress(Ops)` seems to be very close to what this is doing. Except that this API here does not explicitely add a "base" (reg or frame index), but maybe it should start doing that? (So in `foldInlineAsmMemOperand` just remove the register operand (instead of using `ChangeToFrameIndex`) and have this function add the frame index operand as well. That would also help if a target has a different order of operands...

https://github.com/llvm/llvm-project/pull/70832