[llvm] [Mips] In LowerShift*Parts, xor with bits-1 instead of -1. (PR #71149)

[Craig Topper via llvm-commits]

topperc wrote:

There's another bug in this code that neither patch addresses.

I believe this violates the boolean rules. ISD::SELECT should only receive 0/1 as a condition. There needs to be a setcc here.
```
  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,                      
                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 
  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,                                    
                   DAG.getConstant(0, DL, VT), ShiftLeftLo); 
```

https://github.com/llvm/llvm-project/pull/71149