[llvm] [RISCV] Remove experimental- prefix for smaia and ssaia. (PR #71172)
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 3 07:53:26 PDT 2023
https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/71172
>From 71946ef50f3d5c156b9f2627e2eaa315808bd63b Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Fri, 3 Nov 2023 19:01:34 +0800
Subject: [PATCH 1/2] [RISCV] Remove experimental- prefix for smaia and ssaia.
Since smaia and ssaia are ratified now, we could remove their experimental- prefix.
---
llvm/docs/RISCVUsage.rst | 8 ++------
llvm/lib/Support/RISCVISAInfo.cpp | 5 ++---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++----
4 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 7e34269d7acb6f2..e1d5557888bd071 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -90,6 +90,8 @@ on support follow.
``F`` Supported
``H`` Assembly Support
``M`` Supported
+ ``Smaia`` Supported
+ ``Ssaia`` Supported
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
``Svpbmt`` Supported
@@ -188,12 +190,6 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
-``experimental-smaia``
- LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.
-
-``experimental-ssaia``
- LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.
-
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 158ad6fe1d9ca5d..170918eeb18c74b 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -59,6 +59,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"i", RISCVExtensionVersion{2, 1}},
{"m", RISCVExtensionVersion{2, 0}},
+ {"smaia", RISCVExtensionVersion{1, 0}},
+ {"ssaia", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
{"svpbmt", RISCVExtensionVersion{1, 0}},
@@ -166,9 +168,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
- {"smaia", RISCVExtensionVersion{1, 0}},
- {"ssaia", RISCVExtensionVersion{1, 0}},
-
{"zacas", RISCVExtensionVersion{1, 0}},
{"zfbfmin", RISCVExtensionVersion{0, 8}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f078ffd58e5e5e0..6e111f219518b32 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -688,14 +688,14 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtSmaia
- : SubtargetFeature<"experimental-smaia", "HasStdExtSmaia", "true",
+ : SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
"'Smaia' (Smaia encompasses all added CSRs and all "
"modifications to interrupt response behavior that the "
"AIA specifies for a hart, over all privilege levels.)",
[]>;
def FeatureStdExtSsaia
- : SubtargetFeature<"experimental-ssaia", "HasStdExtSsaia", "true",
+ : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Ssaia is essentially the same as Smaia except "
"excluding the machine-level CSRs and behavior not "
"directly visible to supervisor level.)", []>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 33fee2a51c4b3cd..1d987b4c87391aa 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -81,8 +81,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
@@ -171,8 +171,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
>From f903839e956ff72d2d41dc38cd531a15903355e6 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Fri, 3 Nov 2023 22:53:08 +0800
Subject: [PATCH 2/2] Fix llvm/unittests/Support/RISCVISAInfoTest.cpp
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 462f78c94d59b1c..d7f5c5d4ee5e2ca 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -704,6 +704,8 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
+ smaia 1.0
+ ssaia 1.0
svinval 1.0
svnapot 1.0
svpbmt 1.0
@@ -755,8 +757,6 @@ Experimental extensions
zvksg 1.0
zvksh 1.0
zvkt 1.0
- smaia 1.0
- ssaia 1.0
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
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