[PATCH] D86617: [GlobalISel][TableGen] Take first result for multi-output instructions
Bjorn Pettersson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 3 06:04:57 PDT 2023
bjope added inline comments.
================
Comment at: llvm/test/TableGen/GlobalISelEmitter-multiple-output.td:94
+let Defs = [R0] in
+def ImplicitDefInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;
+def OtherInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;
----------------
bjope wrote:
> If we change this into an instruction with two explicit outs it would still pass.
> While I think that it is good to allow having one explicit def and additional implicit-defs, it seems a bit weird to allow multiple explicit outs. Right?
>
> I guess the intent with this patch was to handle the case with implicit defs. But then we still want it to fail when having multiple explicit outs.
> I'm not sure yet how to deal with that.
Maybe we can do something like this to check the number of explicit defs:
```
-static Expected<LLTCodeGen> getInstResultType(const TreePatternNode *Dst) {
+static Expected<LLTCodeGen> getInstResultType(const TreePatternNode *Dst,
+ const CodeGenTarget &Target) {
+ assert(Dst->getOperator()->isSubClassOf("Instruction"));
+ CodeGenInstruction &InstInfo = Target.getInstruction(Dst->getOperator());
+
+ if (InstInfo.Operands.NumDefs != 1)
+ return failedImport("Dst pattern child is not having single result");
+
ArrayRef<TypeSetByHwMode> ChildTypes = Dst->getExtTypes();
```
I'll continue experimenting with that a bit before updating this patch.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D86617/new/
https://reviews.llvm.org/D86617
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