[llvm] [SVE][InstCombine] Fold ld1d and splice into ld1ro (PR #69565)

[via llvm-commits]

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@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mattr=+sve,+f64mm -passes=instcombine -aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-max=512 < %s | FileCheck %s
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vfdff wrote:

Thanks, add attribute `vscale_range(4,4)` for IR, then remove the option `aarch64-sve-vector-bits-max`

https://github.com/llvm/llvm-project/pull/69565