[llvm] [RISCV][GISEL] Add support for lowerFormalArguments that contain scalable vector types (PR #70882)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 2 19:04:37 PDT 2023
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/70882
>From 664f084f108e61e6c94f8f4c8aa0386f71187fcb Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 31 Oct 2023 18:33:47 -0700
Subject: [PATCH 1/8] [CodeGen][MachineVerifier] Use TypeSize instead of
unsigned for getRegSizeInBits
This patch changes getRegSizeInBits to return a TypeSize instead of an
unsigned in the case that a virtual register has a scalable LLT. In the
case that register is physical, a Fixed TypeSize is returned.
The MachineVerifier pass is updated to allow copies between fixed and
scalable operands as long as the Src size will fit into the Dest size.
This is a precommit which will be stacked on by a change to GISel to
generate COPYs with a scalable destination but a fixed size source.
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 6 ++---
llvm/lib/CodeGen/MachineVerifier.cpp | 22 ++++++++++++++-----
llvm/lib/CodeGen/TargetRegisterInfo.cpp | 19 ++++++++--------
3 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 337fab735a09522..4fb6ba7c26930af 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -283,8 +283,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
// DenseMapInfo<unsigned> uses -1u and -2u.
/// Return the size in bits of a register from class RC.
- unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).RegSize;
+ TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const {
+ return TypeSize::Fixed(getRegClassInfo(RC).RegSize);
}
/// Return the size in bytes of the stack slot allocated to hold a spilled
@@ -858,7 +858,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
const TargetRegisterClass *RC) const = 0;
/// Returns size in bits of a phys/virtual/generic register.
- unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
+ TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
/// Get the weight in units of pressure for this register unit.
virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index dadaf60fa09da04..9837a93d8339974 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1937,8 +1937,9 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// If we have only one valid type, this is likely a copy between a virtual
// and physical register.
- unsigned SrcSize = 0;
- unsigned DstSize = 0;
+ TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
+ TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
+
if (SrcReg.isPhysical() && DstTy.isValid()) {
const TargetRegisterClass *SrcRC =
TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
@@ -1946,7 +1947,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
SrcSize = TRI->getRegSizeInBits(*SrcRC);
}
- if (SrcSize == 0)
+ if (SrcSize.isZero())
SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
if (DstReg.isPhysical() && SrcTy.isValid()) {
@@ -1956,10 +1957,21 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
DstSize = TRI->getRegSizeInBits(*DstRC);
}
- if (DstSize == 0)
+ if (DstSize.isZero())
DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
- if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
+ // If the Dst is scalable and the Src is fixed, then the Dst can only hold
+ // the Src if the minimum size Dst can hold is at least as big as Src.
+ if (DstSize.isScalable() && !SrcSize.isScalable() &&
+ DstSize.getKnownMinValue() <= SrcSize.getFixedValue())
+ break;
+ // If the Src is scalable and the Dst is fixed, then Dest can only hold
+ // the Src is known to fit in Dest
+ if (SrcSize.isScalable() && !DstSize.isScalable() &&
+ TypeSize::isKnownLE(DstSize, SrcSize))
+ break;
+
+ if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
report("Copy Instruction is illegal with mismatching sizes", MI);
errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 1bb35f40facfd0f..c50b1cf9422717a 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -499,7 +499,7 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
return true;
}
-unsigned
+TypeSize
TargetRegisterInfo::getRegSizeInBits(Register Reg,
const MachineRegisterInfo &MRI) const {
const TargetRegisterClass *RC{};
@@ -508,16 +508,15 @@ TargetRegisterInfo::getRegSizeInBits(Register Reg,
// Instead, we need to access a register class that contains Reg and
// get the size of that register class.
RC = getMinimalPhysRegClass(Reg);
- } else {
- LLT Ty = MRI.getType(Reg);
- unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
- // If Reg is not a generic register, query the register class to
- // get its size.
- if (RegSize)
- return RegSize;
- // Since Reg is not a generic register, it must have a register class.
- RC = MRI.getRegClass(Reg);
+ assert(RC && "Unable to deduce the register class");
+ return getRegSizeInBits(*RC);
}
+ LLT Ty = MRI.getType(Reg);
+ if (Ty.isValid())
+ return Ty.getSizeInBits();
+
+ // Since Reg is not a generic register, it may have a register class.
+ RC = MRI.getRegClass(Reg);
assert(RC && "Unable to deduce the register class");
return getRegSizeInBits(*RC);
}
>From d4137271fba2b5db04e65c937d83ed9fc7b1c907 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 31 Oct 2023 08:44:51 -0700
Subject: [PATCH 2/8] [RISCV][GISEL] Add support for lowerFormalArguments that
contain scalable vector types
Scalable vector types from LLVM IR can be lowered to scalable vector
types in MIR according to the RISCV::CC_RISCV function.
---
llvm/lib/CodeGen/LowLevelType.cpp | 2 +-
.../Target/RISCV/GISel/RISCVCallLowering.cpp | 7 +
.../RISCV/GlobalISel/irtranslator/vec-args.ll | 693 ++++++++++++++++++
3 files changed, 701 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
diff --git a/llvm/lib/CodeGen/LowLevelType.cpp b/llvm/lib/CodeGen/LowLevelType.cpp
index 24c30b756737b20..cd85bf606989f9e 100644
--- a/llvm/lib/CodeGen/LowLevelType.cpp
+++ b/llvm/lib/CodeGen/LowLevelType.cpp
@@ -17,7 +17,7 @@ using namespace llvm;
LLT::LLT(MVT VT) {
if (VT.isVector()) {
- bool asVector = VT.getVectorMinNumElements() > 1;
+ bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
init(/*IsPointer=*/false, asVector, /*IsScalar=*/!asVector,
VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(),
/*AddressSpace=*/0);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 1806fcf4b5a1664..1fb9c1136addd03 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -14,6 +14,7 @@
#include "RISCVCallLowering.h"
#include "RISCVISelLowering.h"
+#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
@@ -181,6 +182,9 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
const DataLayout &DL = MF.getDataLayout();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+ if (LocVT.isScalableVector())
+ MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
+
return RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
LocInfo, Flags, State, /*IsFixed=*/true, IsRet,
Info.Ty, *Subtarget.getTargetLowering(),
@@ -303,6 +307,9 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget) {
return true;
if (T->isPointerTy())
return true;
+ // TODO: Support fixed vector types.
+ if (T->isVectorTy() && T->isScalableTy() && Subtarget.hasVInstructions())
+ return true;
return false;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
new file mode 100644
index 000000000000000..8dfe00f678622fe
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -0,0 +1,693 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV64 %s
+
+; ==========================================================================
+; ============================= Scalable Types =============================
+; ==========================================================================
+
+define void @test_args_nxv1i8(<vscale x 1 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv1i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2i8(<vscale x 2 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv2i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4i8(<vscale x 4 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv4i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8i8(<vscale x 8 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv8i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv16i8(<vscale x 16 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv16i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv32i8(<vscale x 32 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv32i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv64i8(<vscale x 64 x i8> %a) {
+ ; RV32-LABEL: name: test_args_nxv64i8
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv64i8
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1i16(<vscale x 1 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv1i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2i16(<vscale x 2 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv2i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4i16(<vscale x 4 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv4i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8i16(<vscale x 8 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv8i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv16i16(<vscale x 16 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv16i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv32i16(<vscale x 32 x i16> %a) {
+ ; RV32-LABEL: name: test_args_nxv32i16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1i32(<vscale x 1 x i32> %a) {
+ ; RV32-LABEL: name: test_args_nxv1i32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2i32(<vscale x 2 x i32> %a) {
+ ; RV32-LABEL: name: test_args_nxv2i32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4i32(<vscale x 4 x i32> %a) {
+ ; RV32-LABEL: name: test_args_nxv4i32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8i32(<vscale x 8 x i32> %a) {
+ ; RV32-LABEL: name: test_args_nxv8i32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv16i32(<vscale x 16 x i32> %a) {
+ ; RV32-LABEL: name: test_args_nxv16i32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1i64(<vscale x 1 x i64> %a) {
+ ; RV32-LABEL: name: test_args_nxv1i64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2i64(<vscale x 2 x i64> %a) {
+ ; RV32-LABEL: name: test_args_nxv2i64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4i64(<vscale x 4 x i64> %a) {
+ ; RV32-LABEL: name: test_args_nxv4i64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8i64(<vscale x 8 x i64> %a) {
+ ; RV32-LABEL: name: test_args_nxv8i64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv64i1(<vscale x 64 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv64i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv64i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv32i1(<vscale x 32 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv32i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv16i1(<vscale x 16 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv16i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8i1(<vscale x 8 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv8i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4i1(<vscale x 4 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv4i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2i1(<vscale x 2 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv2i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1i1(<vscale x 1 x i1> %a) {
+ ; RV32-LABEL: name: test_args_nxv1i1
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i1
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1f32(<vscale x 1 x float> %a) {
+ ; RV32-LABEL: name: test_args_nxv1f32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2f32(<vscale x 2 x float> %a) {
+ ; RV32-LABEL: name: test_args_nxv2f32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4f32(<vscale x 4 x float> %a) {
+ ; RV32-LABEL: name: test_args_nxv4f32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8f32(<vscale x 8 x float> %a) {
+ ; RV32-LABEL: name: test_args_nxv8f32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv16f32(<vscale x 16 x float> %a) {
+ ; RV32-LABEL: name: test_args_nxv16f32
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16f32
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv1f64(<vscale x 1 x double> %a) {
+ ; RV32-LABEL: name: test_args_nxv1f64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv2f64(<vscale x 2 x double> %a) {
+ ; RV32-LABEL: name: test_args_nxv2f64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv4f64(<vscale x 4 x double> %a) {
+ ; RV32-LABEL: name: test_args_nxv4f64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
+
+define void @test_args_nxv8f64(<vscale x 8 x double> %a) {
+ ; RV32-LABEL: name: test_args_nxv8f64
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f64
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+entry:
+ ret void
+}
>From 4b1f7e2d91f7a05f6306286ac58af5883a453d9a Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 1 Nov 2023 12:00:46 -0700
Subject: [PATCH 3/8] don't support vectors for lowerCall
---
llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 1fb9c1136addd03..65409e453c43b79 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -298,7 +298,9 @@ RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
: CallLowering(&TLI) {}
// TODO: Support all argument types.
-static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget) {
+// TODO: Remove IsLowerArgs argument by adding support for vectors in lowerCall.
+static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
+ bool IsLowerArgs = false) {
// TODO: Integers larger than 2*XLen are passed indirectly which is not
// supported yet.
if (T->isIntegerTy())
@@ -308,7 +310,8 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget) {
if (T->isPointerTy())
return true;
// TODO: Support fixed vector types.
- if (T->isVectorTy() && T->isScalableTy() && Subtarget.hasVInstructions())
+ if (IsLowerArgs && T->isVectorTy() && T->isScalableTy() &&
+ Subtarget.hasVInstructions())
return true;
return false;
}
@@ -397,7 +400,7 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const RISCVSubtarget &Subtarget =
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
for (auto &Arg : F.args()) {
- if (!isSupportedArgumentType(Arg.getType(), Subtarget))
+ if (!isSupportedArgumentType(Arg.getType(), Subtarget, /*IsLowerArgs*/true))
return false;
}
>From b95492f033215077093c45968ee24acb87dcaeef Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 1 Nov 2023 13:33:37 -0700
Subject: [PATCH 4/8] bail out for 16b fp vector types
---
llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 65409e453c43b79..0f4940794ffa9cc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -309,9 +309,10 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
return true;
if (T->isPointerTy())
return true;
+ // TODO: support 16bit FPtypes.
// TODO: Support fixed vector types.
- if (IsLowerArgs && T->isVectorTy() && T->isScalableTy() &&
- Subtarget.hasVInstructions())
+ if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
+ !T->is16bitFPTy() && T->isScalableTy())
return true;
return false;
}
>From be9a1526d05224be01c6e61d4b1374732433130f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 1 Nov 2023 16:08:32 -0700
Subject: [PATCH 5/8] Add test for half and bfloat vectors
---
.../Target/RISCV/GISel/RISCVCallLowering.cpp | 6 +-
.../RISCV/GlobalISel/irtranslator/vec-args.ll | 60 +++++++++++++++++++
2 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 0f4940794ffa9cc..d9e7fe82b39f1c4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -309,10 +309,9 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
return true;
if (T->isPointerTy())
return true;
- // TODO: support 16bit FPtypes.
// TODO: Support fixed vector types.
if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
- !T->is16bitFPTy() && T->isScalableTy())
+ T->isScalableTy())
return true;
return false;
}
@@ -401,7 +400,8 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const RISCVSubtarget &Subtarget =
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
for (auto &Arg : F.args()) {
- if (!isSupportedArgumentType(Arg.getType(), Subtarget, /*IsLowerArgs*/true))
+ if (!isSupportedArgumentType(Arg.getType(), Subtarget,
+ /*IsLowerArgs=*/true))
return false;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
index 8dfe00f678622fe..97e58cadc9b71fd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -691,3 +691,63 @@ define void @test_args_nxv8f64(<vscale x 8 x double> %a) {
entry:
ret void
}
+
+define void @test_args_nxv1f16(<vscale x 1 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv2f16(<vscale x 2 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv4f16(<vscale x 4 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv8f16(<vscale x 8 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv16f16(<vscale x 16 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv32f16(<vscale x 32 x half> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv1b16(<vscale x 1 x bfloat> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv2b16(<vscale x 2 x bfloat> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv4b16(<vscale x 4 x bfloat> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv8b16(<vscale x 8 x bfloat> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv16b16(<vscale x 16 x bfloat> %a) {
+entry:
+ ret void
+}
+
+define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {
+entry:
+ ret void
+}
>From a9e65fd43702329270b93c6cbbae3397fbf4be82 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 2 Nov 2023 13:04:55 -0700
Subject: [PATCH 6/8] get f16 working
---
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 5 +-
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 23 +-
llvm/lib/CodeGen/MachineVerifier.cpp | 4 +-
.../RISCV/GlobalISel/irtranslator/vec-args.ll | 480 ++++++++++++++++++
4 files changed, 501 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 975787a8f5e734f..158049baa8f5700 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -358,7 +358,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
if (PartLLT.isVector() == LLTy.isVector() &&
PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
(!PartLLT.isVector() ||
- PartLLT.getNumElements() == LLTy.getNumElements()) &&
+ PartLLT.getElementCount() == LLTy.getElementCount()) &&
OrigRegs.size() == 1 && Regs.size() == 1) {
Register SrcReg = Regs[0];
@@ -406,6 +406,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
// If PartLLT is a mismatched vector in both number of elements and element
// size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
// have the same elt type, i.e. v4s32.
+ // TODO: Extend this coersion to element multiples other than just 2.
if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
Regs.size() == 1) {
@@ -472,7 +473,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
} else {
// Vector was split, and elements promoted to a wider type.
// FIXME: Should handle floating point promotions.
- LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
+ LLT BVType = LLT::vector(LLTy.getElementCount(), PartLLT);
auto BV = B.buildBuildVector(BVType, Regs);
B.buildTrunc(OrigRegs[0], BV);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 5b4e2b725e1dd76..bc50322293f0ad5 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -1065,16 +1065,16 @@ void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
#ifndef NDEBUG
if (DstTy.isVector()) {
assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
- assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
+ assert(SrcTy.getElementCount() == DstTy.getElementCount() &&
"different number of elements in a trunc/ext");
} else
assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
if (IsExtend)
- assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
+ assert(TypeSize::isKnownGT(DstTy.getSizeInBits(), SrcTy.getSizeInBits()) &&
"invalid narrowing extend");
else
- assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
+ assert(TypeSize::isKnownLT(DstTy.getSizeInBits(), SrcTy.getSizeInBits()) &&
"invalid widening trunc");
#endif
}
@@ -1281,10 +1281,19 @@ MachineIRBuilder::buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
SrcOps[0].getLLTTy(*getMRI());
}) &&
"type mismatch in input list");
- assert((TypeSize::ScalarTy)SrcOps.size() *
- SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
- DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
- "input scalars do not exactly cover the output vector register");
+ if (DstOps[0].getLLTTy(*getMRI()).isScalable())
+ assert((TypeSize::ScalarTy)SrcOps.size() *
+ SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() >=
+ DstOps[0]
+ .getLLTTy(*getMRI())
+ .getSizeInBits()
+ .getKnownMinValue() &&
+ "input scalars does not cover the output vector register");
+ else
+ assert((TypeSize::ScalarTy)SrcOps.size() *
+ SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
+ DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
+ "input scalars do not exactly cover the output vector register");
break;
}
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 9837a93d8339974..eee4164da04308b 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -965,7 +965,7 @@ bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
return false;
}
- if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
+ if (Ty0.isVector() && Ty0.getElementCount() != Ty1.getElementCount()) {
report("operand types must preserve number of vector elements", MI);
return false;
}
@@ -1435,7 +1435,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
if (DstTy.getElementType() != SrcEltTy)
report("G_BUILD_VECTOR result element type must match source type", MI);
- if (DstTy.getNumElements() != MI->getNumOperands() - 1)
+ if (DstTy.getElementCount().getKnownMinValue() > MI->getNumOperands() - 1)
report("G_BUILD_VECTOR must have an operand for each elemement", MI);
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
index 97e58cadc9b71fd..d6c2b3c824f9b30 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -693,61 +693,541 @@ entry:
}
define void @test_args_nxv1f16(<vscale x 1 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv1f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_BUILD_VECTOR [[COPY]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv2f16(<vscale x 2 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv2f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10, $x11
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10, $x11
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv4f16(<vscale x 4 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv4f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv8f16(<vscale x 8 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv8f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv16f16(<vscale x 16 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv16f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64), [[COPY9]](s64), [[COPY10]](s64), [[COPY11]](s64), [[COPY12]](s64), [[COPY13]](s64), [[COPY14]](s64), [[COPY15]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv32f16(<vscale x 32 x half> %a) {
+ ; RV32-LABEL: name: test_args_nxv32f16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32f16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY16:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY17:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY18:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY19:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY20:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY21:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY22:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY23:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY24:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY25:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY26:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY27:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY28:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY29:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY30:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[COPY31:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64), [[COPY9]](s64), [[COPY10]](s64), [[COPY11]](s64), [[COPY12]](s64), [[COPY13]](s64), [[COPY14]](s64), [[COPY15]](s64), [[COPY16]](s64), [[COPY17]](s64), [[COPY18]](s64), [[COPY19]](s64), [[COPY20]](s64), [[COPY21]](s64), [[COPY22]](s64), [[COPY23]](s64), [[COPY24]](s64), [[COPY25]](s64), [[COPY26]](s64), [[COPY27]](s64), [[COPY28]](s64), [[COPY29]](s64), [[COPY30]](s64), [[COPY31]](s64)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s64>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv1b16(<vscale x 1 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv1b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $f10_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $f10_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv2b16(<vscale x 2 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv2b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $f10_f, $f11_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $f10_f, $f11_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv4b16(<vscale x 4 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv4b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv8b16(<vscale x 8 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv8b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv16b16(<vscale x 16 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv16b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY8]](s64)
+ ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY9]](s64)
+ ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY10]](s64)
+ ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY11]](s64)
+ ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY12]](s64)
+ ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY13]](s64)
+ ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY14]](s64)
+ ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY15]](s64)
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[TRUNC3]](s32), [[TRUNC4]](s32), [[TRUNC5]](s32), [[TRUNC6]](s32), [[TRUNC7]](s32)
+ ; RV64-NEXT: [[TRUNC8:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {
+ ; RV32-LABEL: name: test_args_nxv32b16
+ ; RV32: bb.1.entry:
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15
+ ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.15, align 16)
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14
+ ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.14)
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13
+ ; RV32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.13, align 8)
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12
+ ; RV32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.12)
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11
+ ; RV32-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (s32) from %fixed-stack.11, align 16)
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10
+ ; RV32-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (load (s32) from %fixed-stack.10)
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9
+ ; RV32-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (s32) from %fixed-stack.9, align 8)
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8
+ ; RV32-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (load (s32) from %fixed-stack.8)
+ ; RV32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
+ ; RV32-NEXT: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (load (s32) from %fixed-stack.7, align 16)
+ ; RV32-NEXT: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (load (s32) from %fixed-stack.6)
+ ; RV32-NEXT: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (load (s32) from %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (load (s32) from %fixed-stack.4)
+ ; RV32-NEXT: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (load (s32) from %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (load (s32) from %fixed-stack.2)
+ ; RV32-NEXT: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (load (s32) from %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (load (s32) from %fixed-stack.0)
+ ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
+ ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32b16
+ ; RV64: bb.1.entry:
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
+ ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY8]](s64)
+ ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY9]](s64)
+ ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY10]](s64)
+ ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY11]](s64)
+ ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY12]](s64)
+ ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY13]](s64)
+ ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY14]](s64)
+ ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY15]](s64)
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15
+ ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.15, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14
+ ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.14, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13
+ ; RV64-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.13, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12
+ ; RV64-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.12, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11
+ ; RV64-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (s32) from %fixed-stack.11, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10
+ ; RV64-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (load (s32) from %fixed-stack.10, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9
+ ; RV64-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (s32) from %fixed-stack.9, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8
+ ; RV64-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (load (s32) from %fixed-stack.8, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
+ ; RV64-NEXT: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (load (s32) from %fixed-stack.7, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (load (s32) from %fixed-stack.6, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (load (s32) from %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (load (s32) from %fixed-stack.4, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (load (s32) from %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (load (s32) from %fixed-stack.2, align 8)
+ ; RV64-NEXT: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (load (s32) from %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (load (s32) from %fixed-stack.0, align 8)
+ ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[TRUNC3]](s32), [[TRUNC4]](s32), [[TRUNC5]](s32), [[TRUNC6]](s32), [[TRUNC7]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
+ ; RV64-NEXT: [[TRUNC8:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV64-NEXT: PseudoRET
entry:
ret void
}
>From c31f3e32079e03a21b48ed6046649c60bb47b265 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 2 Nov 2023 18:40:05 -0700
Subject: [PATCH 7/8] check legal rvv types
---
.../Target/RISCV/GISel/RISCVCallLowering.cpp | 31 +-
.../irtranslator/vec-args-bf16-err.ll | 16 +
.../irtranslator/vec-args-f16-err.ll | 16 +
.../RISCV/GlobalISel/irtranslator/vec-args.ll | 428 +++---------------
4 files changed, 114 insertions(+), 377 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index d9e7fe82b39f1c4..f154de69d5c7190 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -297,6 +297,34 @@ struct RISCVCallReturnHandler : public RISCVIncomingValueHandler {
RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
: CallLowering(&TLI) {}
+/// Return true if scalable vector with ScalarTy is legal for lowering.
+static bool isLegalElementTypeForRVV(EVT ScalarTy,
+ const RISCVSubtarget &Subtarget) {
+ if (!ScalarTy.isSimple())
+ return false;
+ switch (ScalarTy.getSimpleVT().SimpleTy) {
+ case MVT::iPTR:
+ return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ return true;
+ case MVT::i64:
+ return Subtarget.hasVInstructionsI64();
+ case MVT::f16:
+ return Subtarget.hasVInstructionsF16();
+ case MVT::bf16:
+ return Subtarget.hasVInstructionsBF16();
+ case MVT::f32:
+ return Subtarget.hasVInstructionsF32();
+ case MVT::f64:
+ return Subtarget.hasVInstructionsF64();
+ default:
+ return false;
+ }
+}
+
// TODO: Support all argument types.
// TODO: Remove IsLowerArgs argument by adding support for vectors in lowerCall.
static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
@@ -311,7 +339,8 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
return true;
// TODO: Support fixed vector types.
if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
- T->isScalableTy())
+ T->isScalableTy() &&
+ isLegalElementTypeForRVV(EVT::getEVT(T->getScalarType()), Subtarget))
return true;
return false;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
new file mode 100644
index 000000000000000..f39e7793e5d4f31
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-bf16-err.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
+
+; The purpose of this test is to show that the compiler throws an error when
+; there is no support for bf16 vectors. If the compiler did not throw an error,
+; then it will try to scalarize the argument to an s32, which may drop elements.
+define void @test_args_nxv1bf16(<vscale x 1 x bfloat> %a) {
+entry:
+ ret void
+}
+
+; CHECK: LLVM ERROR: unable to lower arguments: ptr (in function: test_args_nxv1bf16)
+
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
new file mode 100644
index 000000000000000..042b455bfb54754
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args-f16-err.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck %s
+
+; The purpose of this test is to show that the compiler throws an error when
+; there is no support for f16 vectors. If the compiler did not throw an error,
+; then it will try to scalarize the argument to an s32, which may drop elements.
+define void @test_args_nxv1f16(<vscale x 1 x half> %a) {
+entry:
+ ret void
+}
+
+; CHECK: LLVM ERROR: unable to lower arguments: ptr (in function: test_args_nxv1f16)
+
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
index d6c2b3c824f9b30..b24382a96cdb0e6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
-; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
-; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32,RV32-F16 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64,RV64-F16 %s
; ==========================================================================
; ============================= Scalable Types =============================
@@ -695,20 +695,16 @@ entry:
define void @test_args_nxv1f16(<vscale x 1 x half> %a) {
; RV32-LABEL: name: test_args_nxv1f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_BUILD_VECTOR [[COPY]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -717,22 +713,16 @@ entry:
define void @test_args_nxv2f16(<vscale x 2 x half> %a) {
; RV32-LABEL: name: test_args_nxv2f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10, $x11
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv2f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10, $x11
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -741,26 +731,16 @@ entry:
define void @test_args_nxv4f16(<vscale x 4 x half> %a) {
; RV32-LABEL: name: test_args_nxv4f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv4f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -769,34 +749,16 @@ entry:
define void @test_args_nxv8f16(<vscale x 8 x half> %a) {
; RV32-LABEL: name: test_args_nxv8f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: liveins: $v8m2
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv8f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: liveins: $v8m2
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -805,50 +767,16 @@ entry:
define void @test_args_nxv16f16(<vscale x 16 x half> %a) {
; RV32-LABEL: name: test_args_nxv16f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: liveins: $v8m4
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv16f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: liveins: $v8m4
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64), [[COPY9]](s64), [[COPY10]](s64), [[COPY11]](s64), [[COPY12]](s64), [[COPY13]](s64), [[COPY14]](s64), [[COPY15]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -857,82 +785,16 @@ entry:
define void @test_args_nxv32f16(<vscale x 32 x half> %a) {
; RV32-LABEL: name: test_args_nxv32f16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10
+ ; RV32-NEXT: liveins: $v8m8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv32f16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10
+ ; RV64-NEXT: liveins: $v8m8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY16:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY17:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY18:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY19:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY20:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY21:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY22:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY23:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY24:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY25:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY26:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY27:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY28:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY29:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY30:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[COPY31:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64), [[COPY9]](s64), [[COPY10]](s64), [[COPY11]](s64), [[COPY12]](s64), [[COPY13]](s64), [[COPY14]](s64), [[COPY15]](s64), [[COPY16]](s64), [[COPY17]](s64), [[COPY18]](s64), [[COPY19]](s64), [[COPY20]](s64), [[COPY21]](s64), [[COPY22]](s64), [[COPY23]](s64), [[COPY24]](s64), [[COPY25]](s64), [[COPY26]](s64), [[COPY27]](s64), [[COPY28]](s64), [[COPY29]](s64), [[COPY30]](s64), [[COPY31]](s64)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s64>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -941,20 +803,16 @@ entry:
define void @test_args_nxv1b16(<vscale x 1 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv1b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $f10_f
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $f10_f
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_BUILD_VECTOR [[COPY]](s32)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 1 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -963,22 +821,16 @@ entry:
define void @test_args_nxv2b16(<vscale x 2 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv2b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $f10_f, $f11_f
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv2b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $f10_f, $f11_f
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 2 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -987,26 +839,16 @@ entry:
define void @test_args_nxv4b16(<vscale x 4 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv4b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV32-NEXT: liveins: $v8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv4b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV64-NEXT: liveins: $v8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 4 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -1015,34 +857,16 @@ entry:
define void @test_args_nxv8b16(<vscale x 8 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv8b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: liveins: $v8m2
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv8b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: liveins: $v8m2
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 8 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -1051,58 +875,16 @@ entry:
define void @test_args_nxv16b16(<vscale x 16 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv16b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: liveins: $v8m4
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11
- ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x12
- ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x13
- ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x14
- ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x15
- ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x16
- ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv16b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: liveins: $v8m4
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY8]](s64)
- ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x11
- ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY9]](s64)
- ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x12
- ; RV64-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY10]](s64)
- ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x13
- ; RV64-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY11]](s64)
- ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x14
- ; RV64-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY12]](s64)
- ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x15
- ; RV64-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY13]](s64)
- ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x16
- ; RV64-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY14]](s64)
- ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x17
- ; RV64-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY15]](s64)
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[TRUNC3]](s32), [[TRUNC4]](s32), [[TRUNC5]](s32), [[TRUNC6]](s32), [[TRUNC7]](s32)
- ; RV64-NEXT: [[TRUNC8:%[0-9]+]]:_(<vscale x 16 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 16 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
; RV64-NEXT: PseudoRET
entry:
ret void
@@ -1111,122 +893,16 @@ entry:
define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {
; RV32-LABEL: name: test_args_nxv32b16
; RV32: bb.1.entry:
- ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV32-NEXT: liveins: $v8m8
; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV32-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
- ; RV32-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11
- ; RV32-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x12
- ; RV32-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $x13
- ; RV32-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $x14
- ; RV32-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY $x15
- ; RV32-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY $x16
- ; RV32-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17
- ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15
- ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.15, align 16)
- ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14
- ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.14)
- ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13
- ; RV32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.13, align 8)
- ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12
- ; RV32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.12)
- ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11
- ; RV32-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (s32) from %fixed-stack.11, align 16)
- ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10
- ; RV32-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (load (s32) from %fixed-stack.10)
- ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9
- ; RV32-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (s32) from %fixed-stack.9, align 8)
- ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8
- ; RV32-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (load (s32) from %fixed-stack.8)
- ; RV32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
- ; RV32-NEXT: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (load (s32) from %fixed-stack.7, align 16)
- ; RV32-NEXT: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
- ; RV32-NEXT: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (load (s32) from %fixed-stack.6)
- ; RV32-NEXT: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
- ; RV32-NEXT: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (load (s32) from %fixed-stack.5, align 8)
- ; RV32-NEXT: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
- ; RV32-NEXT: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (load (s32) from %fixed-stack.4)
- ; RV32-NEXT: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; RV32-NEXT: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (load (s32) from %fixed-stack.3, align 16)
- ; RV32-NEXT: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; RV32-NEXT: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (load (s32) from %fixed-stack.2)
- ; RV32-NEXT: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; RV32-NEXT: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (load (s32) from %fixed-stack.1, align 8)
- ; RV32-NEXT: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; RV32-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (load (s32) from %fixed-stack.0)
- ; RV32-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
- ; RV32-NEXT: [[TRUNC:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv32b16
; RV64: bb.1.entry:
- ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
+ ; RV64-NEXT: liveins: $v8m8
; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
- ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
- ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
- ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
- ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
- ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
- ; RV64-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
- ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY8]](s64)
- ; RV64-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY $x11
- ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY9]](s64)
- ; RV64-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $x12
- ; RV64-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY10]](s64)
- ; RV64-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $x13
- ; RV64-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY11]](s64)
- ; RV64-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $x14
- ; RV64-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY12]](s64)
- ; RV64-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $x15
- ; RV64-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY13]](s64)
- ; RV64-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $x16
- ; RV64-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY14]](s64)
- ; RV64-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $x17
- ; RV64-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY15]](s64)
- ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15
- ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.15, align 16)
- ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14
- ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.14, align 8)
- ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13
- ; RV64-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.13, align 16)
- ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12
- ; RV64-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.12, align 8)
- ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11
- ; RV64-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (load (s32) from %fixed-stack.11, align 16)
- ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10
- ; RV64-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (load (s32) from %fixed-stack.10, align 8)
- ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9
- ; RV64-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (load (s32) from %fixed-stack.9, align 16)
- ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8
- ; RV64-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (load (s32) from %fixed-stack.8, align 8)
- ; RV64-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
- ; RV64-NEXT: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (load (s32) from %fixed-stack.7, align 16)
- ; RV64-NEXT: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
- ; RV64-NEXT: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (load (s32) from %fixed-stack.6, align 8)
- ; RV64-NEXT: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
- ; RV64-NEXT: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (load (s32) from %fixed-stack.5, align 16)
- ; RV64-NEXT: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
- ; RV64-NEXT: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (load (s32) from %fixed-stack.4, align 8)
- ; RV64-NEXT: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; RV64-NEXT: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (load (s32) from %fixed-stack.3, align 16)
- ; RV64-NEXT: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; RV64-NEXT: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (load (s32) from %fixed-stack.2, align 8)
- ; RV64-NEXT: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; RV64-NEXT: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (load (s32) from %fixed-stack.1, align 16)
- ; RV64-NEXT: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; RV64-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; RV64-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<vscale x 32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[TRUNC]](s32), [[TRUNC1]](s32), [[TRUNC2]](s32), [[TRUNC3]](s32), [[TRUNC4]](s32), [[TRUNC5]](s32), [[TRUNC6]](s32), [[TRUNC7]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
- ; RV64-NEXT: [[TRUNC8:%[0-9]+]]:_(<vscale x 32 x s16>) = G_TRUNC [[BUILD_VECTOR]](<vscale x 32 x s32>)
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
; RV64-NEXT: PseudoRET
entry:
ret void
>From 4d0455590c1ee16c93d5cb6b18db065e2be133ee Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 2 Nov 2023 19:01:53 -0700
Subject: [PATCH 8/8] use Type instead of EVT
---
.../Target/RISCV/GISel/RISCVCallLowering.cpp | 29 +++++++------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index f154de69d5c7190..cf20746d55b6da6 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -298,31 +298,24 @@ RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
: CallLowering(&TLI) {}
/// Return true if scalable vector with ScalarTy is legal for lowering.
-static bool isLegalElementTypeForRVV(EVT ScalarTy,
+static bool isLegalElementTypeForRVV(Type *EltTy,
const RISCVSubtarget &Subtarget) {
- if (!ScalarTy.isSimple())
- return false;
- switch (ScalarTy.getSimpleVT().SimpleTy) {
- case MVT::iPTR:
+ if (EltTy->isPointerTy())
return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
+ if (EltTy->isIntegerTy(1) || EltTy->isIntegerTy(8) ||
+ EltTy->isIntegerTy(16) || EltTy->isIntegerTy(32))
return true;
- case MVT::i64:
+ if (EltTy->isIntegerTy(64))
return Subtarget.hasVInstructionsI64();
- case MVT::f16:
+ if (EltTy->isHalfTy())
return Subtarget.hasVInstructionsF16();
- case MVT::bf16:
+ if (EltTy->isBFloatTy())
return Subtarget.hasVInstructionsBF16();
- case MVT::f32:
+ if (EltTy->isFloatTy())
return Subtarget.hasVInstructionsF32();
- case MVT::f64:
+ if (EltTy->isDoubleTy())
return Subtarget.hasVInstructionsF64();
- default:
- return false;
- }
+ return false;
}
// TODO: Support all argument types.
@@ -340,7 +333,7 @@ static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
// TODO: Support fixed vector types.
if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
T->isScalableTy() &&
- isLegalElementTypeForRVV(EVT::getEVT(T->getScalarType()), Subtarget))
+ isLegalElementTypeForRVV(T->getScalarType(), Subtarget))
return true;
return false;
}
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