[llvm] [RISCV][GISel] Add helper to convert a LLT size to a RegisterBankInfo::ValueMapping* for FP. (PR #71123)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 2 17:41:10 PDT 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/71123
>From 106f067c3193ff9a446e3cb9d648f9626b00432b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Nov 2023 15:17:40 -0700
Subject: [PATCH 1/3] [RISCV][GISel] Add helper to convert a LLT size to a
RegisterBankInfo::ValueMapping* for FP.
Use this to simplify code.
---
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 43 ++++++-------------
1 file changed, 14 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f005948d2094445..c50602d54a1a676 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -66,6 +66,12 @@ enum ValueMappingsIdx {
FPR32Idx = 7,
FPR64Idx = 10,
};
+
+const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
+ assert(Size == 32 || Size == 64);
+ unsigned Idx = Size == 64 ? PMI_FPR64 : PMI_FPR32;
+ return &ValueMappings[1 + Idx * 3];
+}
} // namespace RISCV
} // namespace llvm
@@ -185,47 +191,26 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- OperandsMapping = Ty.getSizeInBits() == 64
- ? &RISCV::ValueMappings[RISCV::FPR64Idx]
- : &RISCV::ValueMappings[RISCV::FPR32Idx];
+ OperandsMapping = RISCV::getFPValueMapping(Ty.getSizeInBits());
break;
}
case TargetOpcode::G_FMA: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- OperandsMapping =
- Ty.getSizeInBits() == 64
- ? getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR64Idx],
- &RISCV::ValueMappings[RISCV::FPR64Idx],
- &RISCV::ValueMappings[RISCV::FPR64Idx],
- &RISCV::ValueMappings[RISCV::FPR64Idx]})
- : getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR32Idx],
- &RISCV::ValueMappings[RISCV::FPR32Idx],
- &RISCV::ValueMappings[RISCV::FPR32Idx],
- &RISCV::ValueMappings[RISCV::FPR32Idx]});
- break;
- }
- case TargetOpcode::G_FPEXT: {
- LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
- (void)ToTy;
- LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
- (void)FromTy;
- assert(ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32 &&
- "Unsupported size for G_FPEXT");
- OperandsMapping =
- getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR64Idx],
- &RISCV::ValueMappings[RISCV::FPR32Idx]});
+ const RegisterBankInfo::ValueMapping *FPValueMapping =
+ RISCV::getFPValueMapping(Ty.getSizeInBits());
+ OperandsMapping = getOperandsMapping(
+ {FPValueMapping, FPValueMapping, FPValueMapping, FPValueMapping});
break;
}
+ case TargetOpcode::G_FPEXT:
case TargetOpcode::G_FPTRUNC: {
LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
(void)ToTy;
LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
(void)FromTy;
- assert(ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64 &&
- "Unsupported size for G_FPTRUNC");
OperandsMapping =
- getOperandsMapping({&RISCV::ValueMappings[RISCV::FPR32Idx],
- &RISCV::ValueMappings[RISCV::FPR64Idx]});
+ getOperandsMapping({RISCV::getFPValueMapping(ToTy.getSizeInBits()),
+ RISCV::getFPValueMapping(FromTy.getSizeInBits())});
break;
}
default:
>From 581174b8b995a53f86d35bb939729850fd7be44a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Nov 2023 15:27:12 -0700
Subject: [PATCH 2/3] Use ValueMappingsIdx
---
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index c50602d54a1a676..a487d698a9d74b2 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -69,8 +69,8 @@ enum ValueMappingsIdx {
const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
assert(Size == 32 || Size == 64);
- unsigned Idx = Size == 64 ? PMI_FPR64 : PMI_FPR32;
- return &ValueMappings[1 + Idx * 3];
+ unsigned Idx = Size == 64 ? FPR64Idx : FPR32Idx;
+ return &ValueMappings[Idx];
}
} // namespace RISCV
} // namespace llvm
>From 155c125f0da10c09ac2342fbe5f1fc09b1fd94fc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 Nov 2023 17:40:43 -0700
Subject: [PATCH 3/3] make helper static and local to this file.
---
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index a487d698a9d74b2..99d3000568a9f17 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -66,12 +66,6 @@ enum ValueMappingsIdx {
FPR32Idx = 7,
FPR64Idx = 10,
};
-
-const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
- assert(Size == 32 || Size == 64);
- unsigned Idx = Size == 64 ? FPR64Idx : FPR32Idx;
- return &ValueMappings[Idx];
-}
} // namespace RISCV
} // namespace llvm
@@ -109,6 +103,12 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
}
}
+static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
+ assert(Size == 32 || Size == 64);
+ unsigned Idx = Size == 64 ? RISCV::FPR64Idx : RISCV::FPR32Idx;
+ return &RISCV::ValueMappings[Idx];
+}
+
const RegisterBankInfo::InstructionMapping &
RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode();
@@ -191,13 +191,13 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- OperandsMapping = RISCV::getFPValueMapping(Ty.getSizeInBits());
+ OperandsMapping = getFPValueMapping(Ty.getSizeInBits());
break;
}
case TargetOpcode::G_FMA: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
const RegisterBankInfo::ValueMapping *FPValueMapping =
- RISCV::getFPValueMapping(Ty.getSizeInBits());
+ getFPValueMapping(Ty.getSizeInBits());
OperandsMapping = getOperandsMapping(
{FPValueMapping, FPValueMapping, FPValueMapping, FPValueMapping});
break;
@@ -209,8 +209,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
(void)FromTy;
OperandsMapping =
- getOperandsMapping({RISCV::getFPValueMapping(ToTy.getSizeInBits()),
- RISCV::getFPValueMapping(FromTy.getSizeInBits())});
+ getOperandsMapping({getFPValueMapping(ToTy.getSizeInBits()),
+ getFPValueMapping(FromTy.getSizeInBits())});
break;
}
default:
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