[llvm] [RISCV] CSE by swapping conditional branches (PR #71111)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv32 -O2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -O2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
+
+define void @u_case1_a(ptr %a, i32 %b, ptr %c, ptr %d) {
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topperc wrote:

Would adding `signext` attribute to `i32 %b` in all these tests make the output the same for riscv32 and riscv64?

https://github.com/llvm/llvm-project/pull/71111